1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm RPMH RSC
8
9 maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12 description: |
13 Resource Power Manager Hardened (RPMH) is the mechanism for communicating
14 with the hardened resource accelerators on Qualcomm SoCs. Requests to the
15 resources can be written to the Trigger Command Set (TCS) registers and
16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in
17 sequence over an internal bus.
18
19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
20 (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
21 active/wake resource requests. Multiple such DRVs can exist in a SoC and can
22 be written to from Linux. The structure of each DRV follows the same template
23 with a few variations that are captured by the properties here.
24
25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
26 have powered off to facilitate idle power saving. TCS could be classified as::
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
30 CONTROL - Triggered by F/W
31 See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
32
33 The order in which they are described in the DT, should match the hardware
34 configuration.
35
36 Requests can be made for the state of a resource, when the subsystem is
37 active or idle. When all subsystems like Modem, GPU, CPU are idle, the
38 resource state will be an aggregate of the sleep votes from each of those
39 subsystems. Clients may request a sleep value for their shared resources in
40 addition to the active mode requests.
41
42 Drivers that want to use the RSC to communicate with RPMH must specify their
43 bindings as child nodes of the RSC controllers they wish to communicate with.
44
45 properties:
46 compatible:
47 const: qcom,rpmh-rsc
48
49 interrupts:
50 minItems: 1
51 maxItems: 4
52 description:
53 The interrupt that trips when a message complete/response is received for
54 this DRV from the accelerators.
55 Number of interrupts must match number of DRV blocks.
56
57 label:
58 description:
59 Name for the RSC. The name would be used in trace logs.
60
61 qcom,drv-id:
62 $ref: /schemas/types.yaml#/definitions/uint32
63 description:
64 The ID of the DRV in the RSC block that will be used by this controller.
65
66 qcom,tcs-config:
67 $ref: /schemas/types.yaml#/definitions/uint32-matrix
68 minItems: 4
69 maxItems: 4
70 items:
71 items:
72 - description: |
73 TCS type::
74 - ACTIVE_TCS
75 - SLEEP_TCS
76 - WAKE_TCS
77 - CONTROL_TCS
78 enum: [ 0, 1, 2, 3 ]
79 - description: Number of TCS
80 description: |
81 The tuple defining the configuration of TCS. Must have two cells which
82 describe each TCS type. The order of the TCS must match the hardware
83 configuration.
84
85 qcom,tcs-offset:
86 $ref: /schemas/types.yaml#/definitions/uint32
87 description:
88 The offset of the TCS blocks.
89
90 reg:
91 minItems: 1
92 maxItems: 4
93
94 reg-names:
95 minItems: 1
96 items:
97 - const: drv-0
98 - const: drv-1
99 - const: drv-2
100 - const: drv-3
101
102 power-domains:
103 maxItems: 1
104
105 bcm-voter:
106 $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
107
108 clock-controller:
109 $ref: /schemas/clock/qcom,rpmhcc.yaml#
110
111 power-controller:
112 $ref: /schemas/power/qcom,rpmpd.yaml#
113
114 patternProperties:
115 '^regulators(-[0-9])?$':
116 $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
117 unevaluatedProperties: false
118
119 required:
120 - compatible
121 - interrupts
122 - qcom,drv-id
123 - qcom,tcs-config
124 - qcom,tcs-offset
125 - reg
126 - reg-names
127 - power-domains
128
129 additionalProperties: false
130
131 examples:
132 - |
133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
134 // 2, the register offsets for DRV2 start at 0D00, the register
135 // calculations are like this::
136 // DRV0: 0x179C0000
137 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
138 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
139 // TCS-OFFSET: 0xD00
140 #include <dt-bindings/interrupt-controller/arm-gic.h>
141 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
142
143 rsc@179c0000 {
144 compatible = "qcom,rpmh-rsc";
145 reg = <0x179c0000 0x10000>,
146 <0x179d0000 0x10000>,
147 <0x179e0000 0x10000>;
148 reg-names = "drv-0", "drv-1", "drv-2";
149 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
152 label = "apps_rsc";
153 qcom,tcs-offset = <0xd00>;
154 qcom,drv-id = <2>;
155 qcom,tcs-config = <ACTIVE_TCS 2>,
156 <SLEEP_TCS 3>,
157 <WAKE_TCS 3>,
158 <CONTROL_TCS 1>;
159 power-domains = <&CLUSTER_PD>;
160 };
161
162 - |
163 // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
164 // register offsets for DRV0 start at 01C00, the register calculations are
165 // like this::
166 // DRV0: 0xAF20000
167 // TCS-OFFSET: 0x1C00
168 #include <dt-bindings/interrupt-controller/arm-gic.h>
169 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
170
171 rsc@af20000 {
172 compatible = "qcom,rpmh-rsc";
173 reg = <0xaf20000 0x10000>;
174 reg-names = "drv-0";
175 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
176 label = "disp_rsc";
177 qcom,tcs-offset = <0x1c00>;
178 qcom,drv-id = <0>;
179 qcom,tcs-config = <ACTIVE_TCS 0>,
180 <SLEEP_TCS 1>,
181 <WAKE_TCS 1>,
182 <CONTROL_TCS 0>;
183 power-domains = <&CLUSTER_PD>;
184 };
185
186 - |
187 #include <dt-bindings/interrupt-controller/arm-gic.h>
188 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
189 #include <dt-bindings/power/qcom-rpmpd.h>
190
191 rsc@18200000 {
192 compatible = "qcom,rpmh-rsc";
193 reg = <0x18200000 0x10000>,
194 <0x18210000 0x10000>,
195 <0x18220000 0x10000>;
196 reg-names = "drv-0", "drv-1", "drv-2";
197 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
200 label = "apps_rsc";
201 qcom,tcs-offset = <0xd00>;
202 qcom,drv-id = <2>;
203 qcom,tcs-config = <ACTIVE_TCS 2>,
204 <SLEEP_TCS 3>,
205 <WAKE_TCS 3>,
206 <CONTROL_TCS 0>;
207 power-domains = <&CLUSTER_PD>;
208
209 clock-controller {
210 compatible = "qcom,sm8350-rpmh-clk";
211 #clock-cells = <1>;
212 clock-names = "xo";
213 clocks = <&xo_board>;
214 };
215
216 power-controller {
217 compatible = "qcom,sm8350-rpmhpd";
218 #power-domain-cells = <1>;
219 operating-points-v2 = <&rpmhpd_opp_table>;
220
221 rpmhpd_opp_table: opp-table {
222 compatible = "operating-points-v2";
223
224 rpmhpd_opp_ret: opp1 {
225 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
226 };
227
228 rpmhpd_opp_min_svs: opp2 {
229 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
230 };
231
232 rpmhpd_opp_low_svs: opp3 {
233 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
234 };
235
236 rpmhpd_opp_svs: opp4 {
237 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
238 };
239
240 rpmhpd_opp_svs_l1: opp5 {
241 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
242 };
243
244 rpmhpd_opp_nom: opp6 {
245 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
246 };
247
248 rpmhpd_opp_nom_l1: opp7 {
249 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
250 };
251
252 rpmhpd_opp_nom_l2: opp8 {
253 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
254 };
255
256 rpmhpd_opp_turbo: opp9 {
257 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
258 };
259
260 rpmhpd_opp_turbo_l1: opp10 {
261 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
262 };
263 };
264 };
265
266 bcm-voter {
267 compatible = "qcom,bcm-voter";
268 };
269 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.