1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
8
9 maintainers:
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
12 description: |+
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14 a sideband logic handling signals to DWC3 host controller inside
15 USB3.0 component.
16
17 properties:
18 compatible:
19 items:
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
23 - socionext,uniphier-pxs2-dwc3-glue
24 - socionext,uniphier-ld20-dwc3-glue
25 - socionext,uniphier-pxs3-dwc3-glue
26 - socionext,uniphier-nx1-dwc3-glue
27 - const: simple-mfd
28
29 reg:
30 maxItems: 1
31
32 "#address-cells":
33 const: 1
34
35 "#size-cells":
36 const: 1
37
38 ranges: true
39
40 patternProperties:
41 "^reset-controller@[0-9a-f]+$":
42 $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
43
44 "^regulator@[0-9a-f]+$":
45 $ref: /schemas/regulator/socionext,uniphier-regulator.yaml#
46
47 "^phy@[0-9a-f]+$":
48 oneOf:
49 - $ref: /schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
50 - $ref: /schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
51
52 required:
53 - compatible
54 - reg
55
56 additionalProperties: false
57
58 examples:
59 - |
60 usb@65b00000 {
61 compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
62 reg = <0x65b00000 0x400>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 ranges = <0 0x65b00000 0x400>;
66
67 reset-controller@0 {
68 compatible = "socionext,uniphier-ld20-usb3-reset";
69 reg = <0x0 0x4>;
70 #reset-cells = <1>;
71 clock-names = "link";
72 clocks = <&sys_clk 14>;
73 reset-names = "link";
74 resets = <&sys_rst 14>;
75 };
76
77 regulator@100 {
78 compatible = "socionext,uniphier-ld20-usb3-regulator";
79 reg = <0x100 0x10>;
80 clock-names = "link";
81 clocks = <&sys_clk 14>;
82 reset-names = "link";
83 resets = <&sys_rst 14>;
84 };
85
86 phy@200 {
87 compatible = "socionext,uniphier-ld20-usb3-hsphy";
88 reg = <0x200 0x10>;
89 #phy-cells = <0>;
90 clock-names = "link", "phy";
91 clocks = <&sys_clk 14>, <&sys_clk 16>;
92 reset-names = "link", "phy";
93 resets = <&sys_rst 14>, <&sys_rst 16>;
94 };
95
96 phy@300 {
97 compatible = "socionext,uniphier-ld20-usb3-ssphy";
98 reg = <0x300 0x10>;
99 #phy-cells = <0>;
100 clock-names = "link", "phy";
101 clocks = <&sys_clk 14>, <&sys_clk 18>;
102 reset-names = "link", "phy";
103 resets = <&sys_rst 14>, <&sys_rst 18>;
104 };
105 };
106
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