1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Tegra Power Management Controller (PMC)
8
9 maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
12
13 properties:
14 compatible:
15 enum:
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
20 - nvidia,tegra210-pmc
21
22 reg:
23 maxItems: 1
24
25 clock-names:
26 items:
27 # Tegra clock of the same name
28 - const: pclk
29 # 32 KHz clock input
30 - const: clk32k_in
31
32 clocks:
33 maxItems: 2
34
35 '#clock-cells':
36 const: 1
37 description: |
38 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink
39 control which allows 32Khz clock output to Tegra blink pad.
40
41 Consumer of PMC clock should specify the desired clock by having the
42 clock ID in its "clocks" phandle cell with PMC clock provider. See
43 include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs.
44
45 '#interrupt-cells':
46 const: 2
47 description: Specifies number of cells needed to encode an interrupt
48 source.
49
50 interrupt-controller: true
51
52 nvidia,invert-interrupt:
53 $ref: /schemas/types.yaml#/definitions/flag
54 description: Inverts the PMU interrupt signal. The PMU is an external Power
55 Management Unit, whose interrupt output signal is fed into the PMC. This
56 signal is optionally inverted, and then fed into the ARM GIC. The PMC is
57 not involved in the detection or handling of this interrupt signal,
58 merely its inversion.
59
60 nvidia,core-power-req-active-high:
61 $ref: /schemas/types.yaml#/definitions/flag
62 description: core power request active-high
63
64 nvidia,sys-clock-req-active-high:
65 $ref: /schemas/types.yaml#/definitions/flag
66 description: system clock request active-high
67
68 nvidia,combined-power-req:
69 $ref: /schemas/types.yaml#/definitions/flag
70 description: combined power request for CPU and core
71
72 nvidia,cpu-pwr-good-en:
73 $ref: /schemas/types.yaml#/definitions/flag
74 description: CPU power good signal from external PMIC to PMC is enabled
75
76 nvidia,suspend-mode:
77 $ref: /schemas/types.yaml#/definitions/uint32
78 description: the suspend mode that the platform should use
79 oneOf:
80 - description: LP0, CPU + Core voltage off and DRAM in self-refresh
81 const: 0
82 - description: LP1, CPU voltage off and DRAM in self-refresh
83 const: 1
84 - description: LP2, CPU voltage off
85 const: 2
86
87 nvidia,cpu-pwr-good-time:
88 $ref: /schemas/types.yaml#/definitions/uint32
89 description: CPU power good time in microseconds
90
91 nvidia,cpu-pwr-off-time:
92 $ref: /schemas/types.yaml#/definitions/uint32
93 description: CPU power off time in microseconds
94
95 nvidia,core-pwr-good-time:
96 $ref: /schemas/types.yaml#/definitions/uint32-array
97 description: core power good time in microseconds
98 items:
99 - description: oscillator stable time
100 - description: power stable time
101
102 nvidia,core-pwr-off-time:
103 $ref: /schemas/types.yaml#/definitions/uint32
104 description: core power off time in microseconds
105
106 nvidia,lp0-vec:
107 $ref: /schemas/types.yaml#/definitions/uint32-array
108 description: |
109 Starting address and length of LP0 vector. The LP0 vector contains the
110 warm boot code that is executed by AVP when resuming from the LP0 state.
111 The AVP (Audio-Video Processor) is an ARM7 processor and always being
112 the first boot processor when chip is power on or resume from deep sleep
113 mode. When the system is resumed from the deep sleep mode, the warm boot
114 code will restore some PLLs, clocks and then brings up CPU0 for resuming
115 the system.
116 items:
117 - description: starting address of LP0 vector
118 - description: length of LP0 vector
119
120 core-supply:
121 description: phandle to voltage regulator connected to the SoC core power
122 rail
123
124 core-domain:
125 type: object
126 description: The vast majority of hardware blocks of Tegra SoC belong to a
127 core power domain, which has a dedicated voltage rail that powers the
128 blocks.
129 additionalProperties: false
130 properties:
131 operating-points-v2:
132 description: Should contain level, voltages and opp-supported-hw
133 property. The supported-hw is a bitfield indicating SoC speedo or
134 process ID mask.
135
136 "#power-domain-cells":
137 const: 0
138
139 required:
140 - operating-points-v2
141 - "#power-domain-cells"
142
143 i2c-thermtrip:
144 type: object
145 description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode
146 exists, hardware-triggered thermal reset will be enabled.
147 additionalProperties: false
148 properties:
149 nvidia,i2c-controller-id:
150 $ref: /schemas/types.yaml#/definitions/uint32
151 description: ID of I2C controller to send poweroff command to PMU.
152 Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0"
153 of the Tegra K1 Technical Reference Manual.
154
155 nvidia,bus-addr:
156 $ref: /schemas/types.yaml#/definitions/uint32
157 description: bus address of the PMU on the I2C bus
158
159 nvidia,reg-addr:
160 $ref: /schemas/types.yaml#/definitions/uint32
161 description: PMU I2C register address to issue poweroff command
162
163 nvidia,reg-data:
164 $ref: /schemas/types.yaml#/definitions/uint32
165 description: power-off command to write to PMU
166
167 nvidia,pinmux-id:
168 $ref: /schemas/types.yaml#/definitions/uint32
169 description: Pinmux used by the hardware when issuing power-off command.
170 Defaults to 0. Valid values are described in section 12.5.2 "Pinmux
171 Support" of the Tegra4 Technical Reference Manual.
172
173 required:
174 - nvidia,i2c-controller-id
175 - nvidia,bus-addr
176 - nvidia,reg-addr
177 - nvidia,reg-data
178
179 powergates:
180 type: object
181 additionalProperties: false
182 description: |
183 This node contains a hierarchy of power domain nodes, which should match
184 the powergates on the Tegra SoC. Each powergate node represents a power-
185 domain on the Tegra SoC that can be power-gated by the Tegra PMC.
186
187 Hardware blocks belonging to a power domain should contain "power-domains"
188 property that is a phandle pointing to corresponding powergate node.
189
190 The name of the powergate node should be one of the below. Note that not
191 every powergate is applicable to all Tegra devices and the following list
192 shows which powergates are applicable to which devices.
193
194 Please refer to Tegra TRM for mode details on the powergate nodes to use
195 for each power-gate block inside Tegra.
196
197 Name Description Devices Applicable
198 --------------------------------------------------------------
199 3d 3D Graphics Tegra20/114/124/210
200 3d0 3D Graphics 0 Tegra30
201 3d1 3D Graphics 1 Tegra30
202 aud Audio Tegra210
203 dfd Debug Tegra210
204 dis Display A Tegra114/124/210
205 disb Display B Tegra114/124/210
206 heg 2D Graphics Tegra30/114/124/210
207 iram Internal RAM Tegra124/210
208 mpe MPEG Encode All
209 nvdec NVIDIA Video Decode Engine Tegra210
210 nvjpg NVIDIA JPEG Engine Tegra210
211 pcie PCIE Tegra20/30/124/210
212 sata SATA Tegra30/124/210
213 sor Display interfaces Tegra124/210
214 ve2 Video Encode Engine 2 Tegra210
215 venc Video Encode Engine All
216 vdec Video Decode Engine Tegra20/30/114/124
217 vic Video Imaging Compositor Tegra124/210
218 xusba USB Partition A Tegra114/124/210
219 xusbb USB Partition B Tegra114/124/210
220 xusbc USB Partition C Tegra114/124/210
221
222 patternProperties:
223 "^[a-z0-9]+$":
224 type: object
225 additionalProperties: false
226 properties:
227 clocks:
228 minItems: 1
229 maxItems: 10
230
231 resets:
232 minItems: 1
233 maxItems: 8
234
235 power-domains:
236 maxItems: 1
237
238 '#power-domain-cells':
239 const: 0
240 description: Must be 0.
241
242 required:
243 - clocks
244 - resets
245 - '#power-domain-cells'
246
247 pinmux:
248 type: object
249 additionalProperties:
250 type: object
251 description: |
252 This is a pad configuration node. On Tegra SoCs a pad is a set of pins
253 which are configured as a group. The pin grouping is a fixed attribute
254 of the hardware. The PMC can be used to set pad power state and
255 signaling voltage. A pad can be either in active or power down mode.
256 The support for power state and signaling voltage configuration varies
257 depending on the pad in question. 3.3V and 1.8V signaling voltages are
258 supported on pins where software controllable signaling voltage
259 switching is available.
260
261 The pad configuration state nodes are placed under the pmc node and
262 they are referred to by the pinctrl client properties. For more
263 information see:
264
265 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
266
267 The pad name should be used as the value of the pins property in pin
268 configuration nodes.
269
270 The following pads are present on Tegra124 and Tegra132:
271
272 audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi,
273 hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
274 pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
275 usb_bias
276
277 The following pads are present on Tegra210:
278
279 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
280 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio,
281 hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
282 sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias
283 additionalProperties: false
284 properties:
285 pins:
286 $ref: /schemas/types.yaml#/definitions/string-array
287 description: Must contain name of the pad(s) to be configured.
288
289 low-power-enable:
290 $ref: /schemas/types.yaml#/definitions/flag
291 description: Configure the pad into power down mode.
292
293 low-power-disable:
294 $ref: /schemas/types.yaml#/definitions/flag
295 description: Configure the pad into active mode.
296
297 power-source:
298 $ref: /schemas/types.yaml#/definitions/uint32
299 description: |
300 Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
301 TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The
302 values are defined in:
303
304 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
305
306 Power state can be configured on all Tegra124 and Tegra132 pads.
307 None of the Tegra124 or Tegra132 pads support signaling voltage
308 switching. All of the listed Tegra210 pads except pex-cntrl support
309 power state configuration. Signaling voltage switching is supported
310 on the following Tegra210 pads:
311
312 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3,
313 spi, spi-hv, uart
314
315 required:
316 - pins
317
318 required:
319 - compatible
320 - reg
321 - clock-names
322 - clocks
323 - '#clock-cells'
324
325 allOf:
326 - if:
327 properties:
328 compatible:
329 contains:
330 const: nvidia,tegra124-pmc
331 then:
332 properties:
333 pinmux:
334 additionalProperties:
335 type: object
336 properties:
337 pins:
338 items:
339 enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib,
340 dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand,
341 pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
342 sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
343 usb_bias ]
344
345 - if:
346 properties:
347 compatible:
348 contains:
349 const: nvidia,tegra210-pmc
350 then:
351 properties:
352 pinmux:
353 additionalProperties:
354 type: object
355 properties:
356 pins:
357 items:
358 enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie,
359 csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic,
360 dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias,
361 pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
362 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3,
363 usb-bias ]
364
365 additionalProperties: false
366
367 dependencies:
368 nvidia,suspend-mode: ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
369 nvidia,core-pwr-off-time: ["nvidia,core-pwr-good-time"]
370 nvidia,cpu-pwr-off-time: ["nvidia,cpu-pwr-good-time"]
371
372 examples:
373 - |
374 #include <dt-bindings/clock/tegra210-car.h>
375 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
376 #include <dt-bindings/soc/tegra-pmc.h>
377
378 pmc@7000e400 {
379 compatible = "nvidia,tegra210-pmc";
380 reg = <0x7000e400 0x400>;
381 core-supply = <®ulator>;
382 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
383 clock-names = "pclk", "clk32k_in";
384 #clock-cells = <1>;
385
386 nvidia,invert-interrupt;
387 nvidia,suspend-mode = <0>;
388 nvidia,cpu-pwr-good-time = <0>;
389 nvidia,cpu-pwr-off-time = <0>;
390 nvidia,core-pwr-good-time = <4587 3876>;
391 nvidia,core-pwr-off-time = <39065>;
392 nvidia,core-power-req-active-high;
393 nvidia,sys-clock-req-active-high;
394
395 pd_core: core-domain {
396 operating-points-v2 = <&core_opp_table>;
397 #power-domain-cells = <0>;
398 };
399
400 powergates {
401 pd_audio: aud {
402 clocks = <&tegra_car TEGRA210_CLK_APE>,
403 <&tegra_car TEGRA210_CLK_APB2APE>;
404 resets = <&tegra_car 198>;
405 power-domains = <&pd_core>;
406 #power-domain-cells = <0>;
407 };
408
409 pd_xusbss: xusba {
410 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
411 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
412 power-domains = <&pd_core>;
413 #power-domain-cells = <0>;
414 };
415 };
416 };
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