1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek AFE PCM controller for mt8188
8
9 maintainers:
10 - Trevor Wu <trevor.wu@mediatek.com>
11
12 properties:
13 compatible:
14 const: mediatek,mt8188-afe
15
16 reg:
17 maxItems: 1
18
19 interrupts:
20 maxItems: 1
21
22 resets:
23 maxItems: 1
24
25 reset-names:
26 const: audiosys
27
28 memory-region:
29 maxItems: 1
30 description: |
31 Shared memory region for AFE memif. A "shared-dma-pool".
32 See dtschema reserved-memory/shared-dma-pool.yaml for details.
33
34 mediatek,topckgen:
35 $ref: /schemas/types.yaml#/definitions/phandle
36 description: The phandle of the mediatek topckgen controller
37
38 mediatek,infracfg:
39 $ref: /schemas/types.yaml#/definitions/phandle
40 description: The phandle of the mediatek infracfg controller
41
42 power-domains:
43 maxItems: 1
44
45 clocks:
46 items:
47 - description: 26M clock
48 - description: audio pll1 clock
49 - description: audio pll2 clock
50 - description: clock divider for i2si1_mck
51 - description: clock divider for i2si2_mck
52 - description: clock divider for i2so1_mck
53 - description: clock divider for i2so2_mck
54 - description: clock divider for dptx_mck
55 - description: a1sys hoping clock
56 - description: audio intbus clock
57 - description: audio hires clock
58 - description: audio local bus clock
59 - description: mux for dptx_mck
60 - description: mux for i2so1_mck
61 - description: mux for i2so2_mck
62 - description: mux for i2si1_mck
63 - description: mux for i2si2_mck
64 - description: audio 26m clock
65 - description: audio pll1 divide 4
66 - description: audio pll2 divide 4
67 - description: clock divider for iec
68 - description: mux for a2sys clock
69 - description: mux for aud_iec
70
71 clock-names:
72 items:
73 - const: clk26m
74 - const: apll1
75 - const: apll2
76 - const: apll12_div0
77 - const: apll12_div1
78 - const: apll12_div2
79 - const: apll12_div3
80 - const: apll12_div9
81 - const: top_a1sys_hp
82 - const: top_aud_intbus
83 - const: top_audio_h
84 - const: top_audio_local_bus
85 - const: top_dptx
86 - const: top_i2so1
87 - const: top_i2so2
88 - const: top_i2si1
89 - const: top_i2si2
90 - const: adsp_audio_26m
91 - const: apll1_d4
92 - const: apll2_d4
93 - const: apll12_div4
94 - const: top_a2sys
95 - const: top_aud_iec
96
97 mediatek,etdm-in1-cowork-source:
98 $ref: /schemas/types.yaml#/definitions/uint32
99 description:
100 etdm modules can share the same external clock pin. Specify
101 which etdm clock source is required by this etdm in module.
102 enum:
103 - 1 # etdm2_in
104 - 2 # etdm1_out
105 - 3 # etdm2_out
106
107 mediatek,etdm-in2-cowork-source:
108 $ref: /schemas/types.yaml#/definitions/uint32
109 description:
110 etdm modules can share the same external clock pin. Specify
111 which etdm clock source is required by this etdm in module.
112 enum:
113 - 0 # etdm1_in
114 - 2 # etdm1_out
115 - 3 # etdm2_out
116
117 mediatek,etdm-out1-cowork-source:
118 $ref: /schemas/types.yaml#/definitions/uint32
119 description:
120 etdm modules can share the same external clock pin. Specify
121 which etdm clock source is required by this etdm out module.
122 enum:
123 - 0 # etdm1_in
124 - 1 # etdm2_in
125 - 3 # etdm2_out
126
127 mediatek,etdm-out2-cowork-source:
128 $ref: /schemas/types.yaml#/definitions/uint32
129 description:
130 etdm modules can share the same external clock pin. Specify
131 which etdm clock source is required by this etdm out module.
132 enum:
133 - 0 # etdm1_in
134 - 1 # etdm2_in
135 - 2 # etdm1_out
136
137 patternProperties:
138 "^mediatek,etdm-in[1-2]-chn-disabled$":
139 $ref: /schemas/types.yaml#/definitions/uint8-array
140 minItems: 1
141 maxItems: 16
142 description:
143 This is a list of channel IDs which should be disabled.
144 By default, all data received from ETDM pins will be outputted to
145 memory. etdm in supports disable_out in direct mode(w/o interconn),
146 so user can disable the specified channels by the property.
147 uniqueItems: true
148 items:
149 minimum: 0
150 maximum: 15
151
152 "^mediatek,etdm-in[1-2]-multi-pin-mode$":
153 type: boolean
154 description: if present, the etdm data mode is I2S.
155
156 "^mediatek,etdm-out[1-3]-multi-pin-mode$":
157 type: boolean
158 description: if present, the etdm data mode is I2S.
159
160 required:
161 - compatible
162 - reg
163 - interrupts
164 - resets
165 - reset-names
166 - mediatek,topckgen
167 - mediatek,infracfg
168 - power-domains
169 - clocks
170 - clock-names
171
172 additionalProperties: false
173
174 examples:
175 - |
176 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 #include <dt-bindings/interrupt-controller/irq.h>
178
179 afe@10b10000 {
180 compatible = "mediatek,mt8188-afe";
181 reg = <0x10b10000 0x10000>;
182 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
183 resets = <&watchdog 14>;
184 reset-names = "audiosys";
185 memory-region = <&snd_dma_mem_reserved>;
186 mediatek,topckgen = <&topckgen>;
187 mediatek,infracfg = <&infracfg_ao>;
188 power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO
189 mediatek,etdm-in2-cowork-source = <2>;
190 mediatek,etdm-out2-cowork-source = <0>;
191 mediatek,etdm-in1-multi-pin-mode;
192 mediatek,etdm-in1-chn-disabled = /bits/ 8 <0x0 0x2>;
193 clocks = <&clk26m>,
194 <&apmixedsys 9>, //CLK_APMIXED_APLL1
195 <&apmixedsys 10>, //CLK_APMIXED_APLL2
196 <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
197 <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
198 <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
199 <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3
200 <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9
201 <&topckgen 83>, //CLK_TOP_A1SYS_HP
202 <&topckgen 31>, //CLK_TOP_AUD_INTBUS
203 <&topckgen 32>, //CLK_TOP_AUDIO_H
204 <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS
205 <&topckgen 81>, //CLK_TOP_DPTX
206 <&topckgen 77>, //CLK_TOP_I2SO1
207 <&topckgen 78>, //CLK_TOP_I2SO2
208 <&topckgen 79>, //CLK_TOP_I2SI1
209 <&topckgen 80>, //CLK_TOP_I2SI2
210 <&adsp_audio26m 0>, //CLK_AUDIODSP_AUDIO26M
211 <&topckgen 132>, //CLK_TOP_APLL1_D4
212 <&topckgen 133>, //CLK_TOP_APLL2_D4
213 <&topckgen 183>, //CLK_TOP_APLL12_CK_DIV4
214 <&topckgen 84>, //CLK_TOP_A2SYS
215 <&topckgen 82>; //CLK_TOP_AUD_IEC>;
216 clock-names = "clk26m",
217 "apll1",
218 "apll2",
219 "apll12_div0",
220 "apll12_div1",
221 "apll12_div2",
222 "apll12_div3",
223 "apll12_div9",
224 "top_a1sys_hp",
225 "top_aud_intbus",
226 "top_audio_h",
227 "top_audio_local_bus",
228 "top_dptx",
229 "top_i2so1",
230 "top_i2so2",
231 "top_i2si1",
232 "top_i2si2",
233 "adsp_audio_26m",
234 "apll1_d4",
235 "apll2_d4",
236 "apll12_div4",
237 "top_a2sys",
238 "top_aud_iec";
239 };
240
241 ...
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