1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8365-afe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek Audio Front End PCM controller for MT8365
8
9 maintainers:
10 - Alexandre Mergnat <amergnat@baylibre.com>
11
12 properties:
13 compatible:
14 const: mediatek,mt8365-afe-pcm
15
16 reg:
17 maxItems: 1
18
19 "#sound-dai-cells":
20 const: 0
21
22 clocks:
23 items:
24 - description: 26M clock
25 - description: mux for audio clock
26 - description: audio i2s0 mck
27 - description: audio i2s1 mck
28 - description: audio i2s2 mck
29 - description: audio i2s3 mck
30 - description: engen 1 clock
31 - description: engen 2 clock
32 - description: audio 1 clock
33 - description: audio 2 clock
34 - description: mux for i2s0
35 - description: mux for i2s1
36 - description: mux for i2s2
37 - description: mux for i2s3
38
39 clock-names:
40 items:
41 - const: top_clk26m_clk
42 - const: top_audio_sel
43 - const: audio_i2s0_m
44 - const: audio_i2s1_m
45 - const: audio_i2s2_m
46 - const: audio_i2s3_m
47 - const: engen1
48 - const: engen2
49 - const: aud1
50 - const: aud2
51 - const: i2s0_m_sel
52 - const: i2s1_m_sel
53 - const: i2s2_m_sel
54 - const: i2s3_m_sel
55
56 interrupts:
57 maxItems: 1
58
59 power-domains:
60 maxItems: 1
61
62 mediatek,dmic-mode:
63 $ref: /schemas/types.yaml#/definitions/uint32
64 description:
65 Indicates how many data pins are used to transmit two channels of PDM
66 signal. 1 means two wires, 0 means one wire. Default value is 0.
67 enum:
68 - 0 # one wire
69 - 1 # two wires
70
71 required:
72 - compatible
73 - reg
74 - clocks
75 - clock-names
76 - interrupts
77 - power-domains
78
79 additionalProperties: false
80
81 examples:
82 - |
83 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
84 #include <dt-bindings/interrupt-controller/arm-gic.h>
85 #include <dt-bindings/interrupt-controller/irq.h>
86 #include <dt-bindings/power/mediatek,mt8365-power.h>
87
88 soc {
89 #address-cells = <2>;
90 #size-cells = <2>;
91
92 audio-controller@11220000 {
93 compatible = "mediatek,mt8365-afe-pcm";
94 reg = <0 0x11220000 0 0x1000>;
95 #sound-dai-cells = <0>;
96 clocks = <&clk26m>,
97 <&topckgen CLK_TOP_AUDIO_SEL>,
98 <&topckgen CLK_TOP_AUD_I2S0_M>,
99 <&topckgen CLK_TOP_AUD_I2S1_M>,
100 <&topckgen CLK_TOP_AUD_I2S2_M>,
101 <&topckgen CLK_TOP_AUD_I2S3_M>,
102 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
103 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
104 <&topckgen CLK_TOP_AUD_1_SEL>,
105 <&topckgen CLK_TOP_AUD_2_SEL>,
106 <&topckgen CLK_TOP_APLL_I2S0_SEL>,
107 <&topckgen CLK_TOP_APLL_I2S1_SEL>,
108 <&topckgen CLK_TOP_APLL_I2S2_SEL>,
109 <&topckgen CLK_TOP_APLL_I2S3_SEL>;
110 clock-names = "top_clk26m_clk",
111 "top_audio_sel",
112 "audio_i2s0_m",
113 "audio_i2s1_m",
114 "audio_i2s2_m",
115 "audio_i2s3_m",
116 "engen1",
117 "engen2",
118 "aud1",
119 "aud2",
120 "i2s0_m_sel",
121 "i2s1_m_sel",
122 "i2s2_m_sel",
123 "i2s3_m_sel";
124 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
125 power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>;
126 mediatek,dmic-mode = <1>;
127 };
128 };
129
130 ...
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