1 Mediatek AFE PCM controller for mt6797
2
3 Required properties:
4 - compatible = "mediatek,mt6797-audio";
5 - reg: register location and size
6 - interrupts: should contain AFE interrupt
7 - power-domains: should define the power domain
8 - clocks: Must contain an entry for each entry in clock-names
9 - clock-names: should have these clock names:
10 "infra_sys_audio_clk",
11 "infra_sys_audio_26m",
12 "mtkaif_26m_clk",
13 "top_mux_audio",
14 "top_mux_aud_intbus",
15 "top_sys_pll3_d4",
16 "top_sys_pll1_d4",
17 "top_clk26m_clk";
18
19 Example:
20
21 afe: mt6797-afe-pcm@11220000 {
22 compatible = "mediatek,mt6797-audio";
23 reg = <0 0x11220000 0 0x1000>;
24 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>;
25 power-domains = <&scpsys MT6797_POWER_DOMAIN_AUDIO>;
26 clocks = <&infrasys CLK_INFRA_AUDIO>,
27 <&infrasys CLK_INFRA_AUDIO_26M>,
28 <&infrasys CLK_INFRA_AUDIO_26M_PAD_TOP>,
29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
33 <&clk26m>;
34 clock-names = "infra_sys_audio_clk",
35 "infra_sys_audio_26m",
36 "mtkaif_26m_clk",
37 "top_mux_audio",
38 "top_mux_aud_intbus",
39 "top_sys_pll3_d4",
40 "top_sys_pll1_d4",
41 "top_clk26m_clk";
42 };
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