1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
8
9 maintainers:
10 - Biju Das <biju.das.jz@bp.renesas.com>
11
12 allOf:
13 - $ref: dai-common.yaml#
14
15 properties:
16 compatible:
17 items:
18 - enum:
19 - renesas,r9a07g043-ssi # RZ/G2UL and RZ/Five
20 - renesas,r9a07g044-ssi # RZ/G2{L,LC}
21 - renesas,r9a07g054-ssi # RZ/V2L
22 - const: renesas,rz-ssi
23
24 reg:
25 maxItems: 1
26
27 interrupts:
28 minItems: 2
29 maxItems: 3
30
31 interrupt-names:
32 oneOf:
33 - items:
34 - const: int_req
35 - const: dma_rx
36 - const: dma_tx
37 - items:
38 - const: int_req
39 - const: dma_rt
40
41 clocks:
42 maxItems: 4
43
44 clock-names:
45 items:
46 - const: ssi
47 - const: ssi_sfr
48 - const: audio_clk1
49 - const: audio_clk2
50
51 power-domains:
52 maxItems: 1
53
54 resets:
55 maxItems: 1
56
57 dmas:
58 minItems: 1
59 maxItems: 2
60 description:
61 The first cell represents a phandle to dmac.
62 The second cell specifies the encoded MID/RID values of the SSI port
63 connected to the DMA client and the slave channel configuration
64 parameters.
65 bits[0:9] - Specifies MID/RID value of a SSI channel as below
66 MID/RID value of SSI rx0 = 0x256
67 MID/RID value of SSI tx0 = 0x255
68 MID/RID value of SSI rx1 = 0x25a
69 MID/RID value of SSI tx1 = 0x259
70 MID/RID value of SSI rt2 = 0x25f
71 MID/RID value of SSI rx3 = 0x262
72 MID/RID value of SSI tx3 = 0x261
73 bit[10] - HIEN = 1, Detects a request in response to the rising edge
74 of the signal
75 bit[11] - LVL = 0, Detects based on the edge
76 bits[12:14] - AM = 2, Bus cycle mode
77 bit[15] - TM = 0, Single transfer mode
78
79 dma-names:
80 oneOf:
81 - items:
82 - const: tx
83 - const: rx
84 - items:
85 - const: rt
86
87 '#sound-dai-cells':
88 const: 0
89
90 port:
91 $ref: audio-graph-port.yaml#/definitions/port-base
92 description: Connection to controller providing I2S signals
93
94 required:
95 - compatible
96 - reg
97 - interrupts
98 - interrupt-names
99 - clocks
100 - clock-names
101 - resets
102 - '#sound-dai-cells'
103
104 unevaluatedProperties: false
105
106 examples:
107 - |
108 #include <dt-bindings/interrupt-controller/arm-gic.h>
109 #include <dt-bindings/clock/r9a07g044-cpg.h>
110
111 ssi0: ssi@10049c00 {
112 compatible = "renesas,r9a07g044-ssi",
113 "renesas,rz-ssi";
114 reg = <0x10049c00 0x400>;
115 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
117 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
118 interrupt-names = "int_req", "dma_rx", "dma_tx";
119 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
120 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
121 <&audio_clk1>,
122 <&audio_clk2>;
123 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
124 power-domains = <&cpg>;
125 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
126 dmas = <&dmac 0x2655>,
127 <&dmac 0x2656>;
128 dma-names = "tx", "rx";
129 #sound-dai-cells = <0>;
130 };
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