1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,rk3308-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Rockchip RK3308 Internal Codec
8
9 description: |
10 This is the audio codec embedded in the Rockchip RK3308
11 SoC. It has 8 24-bit ADCs and 2 24-bit DACs. The maximum supported
12 sampling rate is 192 kHz.
13
14 It is connected internally to one out of a selection of the internal I2S
15 controllers.
16
17 The RK3308 audio codec has 8 independent capture channels, but some
18 features work on stereo pairs called groups:
19 * grp 0 -- MIC1 / MIC2
20 * grp 1 -- MIC3 / MIC4
21 * grp 2 -- MIC5 / MIC6
22 * grp 3 -- MIC7 / MIC8
23
24 maintainers:
25 - Luca Ceresoli <luca.ceresoli@bootlin.com>
26
27 properties:
28 compatible:
29 const: rockchip,rk3308-codec
30
31 reg:
32 maxItems: 1
33
34 rockchip,grf:
35 $ref: /schemas/types.yaml#/definitions/phandle
36 description:
37 Phandle to the General Register Files (GRF)
38
39 clocks:
40 items:
41 - description: clock for TX
42 - description: clock for RX
43 - description: AHB clock driving the interface
44
45 clock-names:
46 items:
47 - const: mclk_tx
48 - const: mclk_rx
49 - const: hclk
50
51 port:
52 $ref: audio-graph-port.yaml#
53 unevaluatedProperties: false
54
55 resets:
56 maxItems: 1
57
58 reset-names:
59 items:
60 - const: codec
61
62 "#sound-dai-cells":
63 const: 0
64
65 rockchip,micbias-avdd-percent:
66 description: |
67 Voltage setting for the MICBIAS pins expressed as a percentage of
68 AVDD.
69
70 E.g. if rockchip,micbias-avdd-percent = 85 and AVDD = 3v3, then the
71 MIC BIAS voltage will be 3.3 V * 85% = 2.805 V.
72
73 enum: [ 50, 55, 60, 65, 70, 75, 80, 85 ]
74
75 required:
76 - compatible
77 - reg
78 - rockchip,grf
79 - clocks
80 - resets
81 - "#sound-dai-cells"
82
83 additionalProperties: false
84
85 examples:
86 - |
87 #include <dt-bindings/clock/rk3308-cru.h>
88
89 audio_codec: audio-codec@ff560000 {
90 compatible = "rockchip,rk3308-codec";
91 reg = <0xff560000 0x10000>;
92 rockchip,grf = <&grf>;
93 clock-names = "mclk_tx", "mclk_rx", "hclk";
94 clocks = <&cru SCLK_I2S2_8CH_TX_OUT>,
95 <&cru SCLK_I2S2_8CH_RX_OUT>,
96 <&cru PCLK_ACODEC>;
97 reset-names = "codec";
98 resets = <&cru SRST_ACODEC_P>;
99 #sound-dai-cells = <0>;
100 };
101
102 ...
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