1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7
8 title: Atmel SPI device
9
10 maintainers:
11 - Tudor Ambarus <tudor.ambarus@linaro.org>
12
13 allOf:
14 - $ref: spi-controller.yaml#
15
16 properties:
17 compatible:
18 oneOf:
19 - const: atmel,at91rm9200-spi
20 - items:
21 - enum:
22 - microchip,sam9x60-spi
23 - microchip,sam9x7-spi
24 - microchip,sama7d65-spi
25 - const: atmel,at91rm9200-spi
26
27 reg:
28 maxItems: 1
29
30 interrupts:
31 maxItems: 1
32
33 clock-names:
34 contains:
35 const: spi_clk
36
37 clocks:
38 maxItems: 1
39
40 dmas:
41 items:
42 - description: TX DMA Channel
43 - description: RX DMA Channel
44
45 dma-names:
46 items:
47 - const: tx
48 - const: rx
49
50 atmel,fifo-size:
51 $ref: /schemas/types.yaml#/definitions/uint32
52 description: |
53 Maximum number of data the RX and TX FIFOs can store for FIFO
54 capable SPI controllers.
55 enum: [ 16, 32 ]
56
57 required:
58 - compatible
59 - reg
60 - interrupts
61 - clock-names
62 - clocks
63
64 unevaluatedProperties: false
65
66 examples:
67 - |
68 #include <dt-bindings/gpio/gpio.h>
69 #include <dt-bindings/interrupt-controller/irq.h>
70
71 spi1: spi@fffcc000 {
72 compatible = "atmel,at91rm9200-spi";
73 reg = <0xfffcc000 0x4000>;
74 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
75 #address-cells = <1>;
76 #size-cells = <0>;
77 clocks = <&spi1_clk>;
78 clock-names = "spi_clk";
79 cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
80 atmel,fifo-size = <32>;
81
82 mmc@0 {
83 compatible = "mmc-spi-slot";
84 reg = <0>;
85 gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; /* CD */
86 spi-max-frequency = <25000000>;
87 };
88 };
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