1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Broadcom SPI controller
8
9 maintainers:
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
12
13 description: |
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
16 of:
17 MSPI : SPI master controller can read and write to a SPI slave device
18 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
19 for flash reads and be configured to do single, double, quad lane
20 io with 3-byte and 4-byte addressing support.
21
22 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
23 MSPI master can be used without BSPI. BRCMSTB SoCs have an additional instance
24 of a MSPI master without the BSPI to use with non flash slave devices that
25 use SPI protocol.
26
27 allOf:
28 - $ref: spi-controller.yaml#
29
30 properties:
31 compatible:
32 oneOf:
33 - description: Second Instance of MSPI BRCMSTB SoCs
34 items:
35 - enum:
36 - brcm,spi-bcm7425-qspi
37 - brcm,spi-bcm7429-qspi
38 - brcm,spi-bcm7435-qspi
39 - brcm,spi-bcm7445-qspi
40 - brcm,spi-bcm7216-qspi
41 - brcm,spi-bcm7278-qspi
42 - const: brcm,spi-bcm-qspi
43 - const: brcm,spi-brcmstb-mspi
44 - description: Second Instance of MSPI BRCMSTB SoCs
45 items:
46 - enum:
47 - brcm,spi-brcmstb-qspi
48 - brcm,spi-brcmstb-mspi
49 - brcm,spi-nsp-qspi
50 - brcm,spi-ns2-qspi
51 - const: brcm,spi-bcm-qspi
52
53 reg:
54 minItems: 1
55 maxItems: 5
56
57 reg-names:
58 minItems: 1
59 items:
60 - const: mspi
61 - const: bspi
62 - enum: [ intr_regs, intr_status_reg, cs_reg ]
63 - enum: [ intr_regs, intr_status_reg, cs_reg ]
64 - enum: [ intr_regs, intr_status_reg, cs_reg ]
65
66 interrupts:
67 minItems: 1
68 maxItems: 7
69
70 interrupt-names:
71 oneOf:
72 - minItems: 1
73 items:
74 - const: mspi_done
75 - const: mspi_halted
76 - const: spi_lr_fullness_reached
77 - const: spi_lr_session_aborted
78 - const: spi_lr_impatient
79 - const: spi_lr_session_done
80 - const: spi_lr_overread
81 - const: spi_l1_intr
82
83 clocks:
84 maxItems: 1
85 description: reference clock for this block
86
87 native-endian:
88 $ref: /schemas/types.yaml#/definitions/flag
89 description: Defined when using BE SoC and device uses BE register read/write
90
91 unevaluatedProperties: false
92
93 required:
94 - reg
95 - reg-names
96 - interrupts
97 - interrupt-names
98
99 examples:
100 - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access
101 spi@f03e3400 {
102 compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
103 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
104 reg-names = "mspi", "bspi", "cs_reg";
105 interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
106 interrupt-parent = <&gic>;
107 interrupt-names = "mspi_done",
108 "mspi_halted",
109 "spi_lr_fullness_reached",
110 "spi_lr_session_aborted",
111 "spi_lr_impatient",
112 "spi_lr_session_done",
113 "spi_lr_overread";
114 clocks = <&hif_spi>;
115 #address-cells = <0x1>;
116 #size-cells = <0x0>;
117
118 flash@0 {
119 #size-cells = <0x2>;
120 #address-cells = <0x2>;
121 compatible = "m25p80";
122 reg = <0x0>;
123 spi-max-frequency = <0x2625a00>;
124 spi-cpol;
125 spi-cpha;
126 };
127 };
128 - | # BRCMSTB SoC: MSPI master for any SPI device
129 spi@f0416000 {
130 clocks = <&upg_fixed>;
131 compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
132 reg = <0xf0416000 0x180>;
133 reg-names = "mspi";
134 interrupts = <0x14>;
135 interrupt-parent = <&irq0_aon_intc>;
136 interrupt-names = "mspi_done";
137 #address-cells = <1>;
138 #size-cells = <0>;
139 };
140 - | # iProc SoC
141 #include <dt-bindings/interrupt-controller/irq.h>
142 #include <dt-bindings/interrupt-controller/arm-gic.h>
143
144 spi@18027200 {
145 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
146 reg = <0x18027200 0x184>,
147 <0x18027000 0x124>,
148 <0x1811c408 0x004>,
149 <0x180273a0 0x01c>;
150 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
151 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
158 interrupt-names = "mspi_done",
159 "mspi_halted",
160 "spi_lr_fullness_reached",
161 "spi_lr_session_aborted",
162 "spi_lr_impatient",
163 "spi_lr_session_done";
164 clocks = <&iprocmed>;
165 num-cs = <2>;
166 #address-cells = <1>;
167 #size-cells = <0>;
168 };
169 - | # NS2 SoC
170 #include <dt-bindings/interrupt-controller/irq.h>
171 #include <dt-bindings/interrupt-controller/arm-gic.h>
172
173 spi@66470200 {
174 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
175 reg = <0x66470200 0x184>,
176 <0x66470000 0x124>,
177 <0x67017408 0x004>,
178 <0x664703a0 0x01c>;
179 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
180 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
181 interrupt-names = "spi_l1_intr";
182 clocks = <&iprocmed>;
183 num-cs = <2>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186
187 flash@0 {
188 #address-cells = <1>;
189 #size-cells = <1>;
190 compatible = "m25p80";
191 reg = <0x0>;
192 spi-max-frequency = <12500000>;
193 spi-cpol;
194 spi-cpha;
195 };
196 };
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