1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Freescale Quad Serial Peripheral Interface (QuadSPI)
8
9 maintainers:
10 - Han Xu <han.xu@nxp.com>
11
12 allOf:
13 - $ref: spi-controller.yaml#
14
15 properties:
16 compatible:
17 oneOf:
18 - enum:
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
21 - fsl,imx7d-qspi
22 - fsl,imx6ul-qspi
23 - fsl,ls1021a-qspi
24 - fsl,ls2080a-qspi
25 - items:
26 - enum:
27 - fsl,ls1043a-qspi
28 - const: fsl,ls1021a-qspi
29 - items:
30 - enum:
31 - fsl,imx8mq-qspi
32 - const: fsl,imx7d-qspi
33
34 reg:
35 items:
36 - description: registers
37 - description: memory mapping
38
39 reg-names:
40 items:
41 - const: QuadSPI
42 - const: QuadSPI-memory
43
44 interrupts:
45 maxItems: 1
46
47 clocks:
48 items:
49 - description: SoC SPI qspi_en clock
50 - description: SoC SPI qspi clock
51
52 clock-names:
53 items:
54 - const: qspi_en
55 - const: qspi
56
57 required:
58 - compatible
59 - reg
60 - reg-names
61 - interrupts
62 - clocks
63 - clock-names
64
65 unevaluatedProperties: false
66
67 examples:
68 - |
69 #include <dt-bindings/interrupt-controller/arm-gic.h>
70 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
71
72 soc {
73 #address-cells = <2>;
74 #size-cells = <2>;
75
76 spi@1550000 {
77 compatible = "fsl,ls1021a-qspi";
78 reg = <0x0 0x1550000 0x0 0x100000>,
79 <0x0 0x40000000 0x0 0x10000000>;
80 reg-names = "QuadSPI", "QuadSPI-memory";
81 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
82 #address-cells = <1>;
83 #size-cells = <0>;
84 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>,
85 <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>;
86 clock-names = "qspi_en", "qspi";
87
88 flash@0 {
89 compatible = "jedec,spi-nor";
90 spi-max-frequency = <50000000>;
91 reg = <0>;
92 spi-rx-bus-width = <4>;
93 spi-tx-bus-width = <4>;
94 };
95 };
96 };
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