1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Serial NOR flash controller for MediaTek ARM SoCs
8
9 maintainers:
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
12
13 description: |
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
17 for devices other than SPI NOR flash due to limited transfer
18 capability of this controller.
19
20 allOf:
21 - $ref: /schemas/spi/spi-controller.yaml#
22
23 properties:
24 compatible:
25 oneOf:
26 - enum:
27 - mediatek,mt8173-nor
28 - mediatek,mt8186-nor
29 - mediatek,mt8192-nor
30 - items:
31 - enum:
32 - mediatek,mt2701-nor
33 - mediatek,mt2712-nor
34 - mediatek,mt7622-nor
35 - mediatek,mt7623-nor
36 - mediatek,mt7629-nor
37 - mediatek,mt8195-nor
38 - const: mediatek,mt8173-nor
39 - items:
40 - enum:
41 - mediatek,mt8188-nor
42 - const: mediatek,mt8186-nor
43
44 reg:
45 maxItems: 1
46
47 interrupts:
48 maxItems: 1
49
50 clocks:
51 minItems: 2
52 items:
53 - description: clock used for spi bus
54 - description: clock used for controller
55 - description: clock used for nor dma bus. this depends on hardware
56 design, so this is optional.
57 - description: clock used for controller axi slave bus.
58 this depends on hardware design, so it is optional.
59
60 clock-names:
61 minItems: 2
62 items:
63 - const: spi
64 - const: sf
65 - const: axi
66 - const: axi_s
67
68 required:
69 - compatible
70 - reg
71 - clocks
72 - clock-names
73
74 unevaluatedProperties: false
75
76 examples:
77 - |
78 #include <dt-bindings/clock/mt8173-clk.h>
79
80 soc {
81 #address-cells = <2>;
82 #size-cells = <2>;
83
84 nor_flash: spi@1100d000 {
85 compatible = "mediatek,mt8173-nor";
86 reg = <0 0x1100d000 0 0xe0>;
87 interrupts = <1>;
88 clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
89 <&pericfg CLK_PERI_NFI>;
90 clock-names = "spi", "sf", "axi";
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 flash@0 {
95 compatible = "jedec,spi-nor";
96 reg = <0>;
97 };
98 };
99 };
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