1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI)
8
9 maintainers:
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Patrice Chotard <patrice.chotard@foss.st.com>
12
13 allOf:
14 - $ref: spi-controller.yaml#
15
16 properties:
17 compatible:
18 const: st,stm32f469-qspi
19
20 reg:
21 items:
22 - description: registers
23 - description: memory mapping
24
25 reg-names:
26 items:
27 - const: qspi
28 - const: qspi_mm
29
30 clocks:
31 maxItems: 1
32
33 interrupts:
34 maxItems: 1
35
36 resets:
37 maxItems: 1
38
39 dmas:
40 items:
41 - description: tx DMA channel
42 - description: rx DMA channel
43
44 dma-names:
45 items:
46 - const: tx
47 - const: rx
48
49 access-controllers:
50 minItems: 1
51 maxItems: 2
52
53 required:
54 - compatible
55 - reg
56 - reg-names
57 - clocks
58 - interrupts
59
60 unevaluatedProperties: false
61
62 examples:
63 - |
64 #include <dt-bindings/interrupt-controller/arm-gic.h>
65 #include <dt-bindings/clock/stm32mp1-clks.h>
66 #include <dt-bindings/reset/stm32mp1-resets.h>
67 spi@58003000 {
68 compatible = "st,stm32f469-qspi";
69 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
70 reg-names = "qspi", "qspi_mm";
71 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
72 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
73 <&mdma1 22 0x10 0x100008 0x0 0x0>;
74 dma-names = "tx", "rx";
75 clocks = <&rcc QSPI_K>;
76 resets = <&rcc QSPI_R>;
77
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 flash@0 {
82 compatible = "jedec,spi-nor";
83 reg = <0>;
84 spi-rx-bus-width = <4>;
85 spi-max-frequency = <108000000>;
86 };
87 };
88
89 ...
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