1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spi/ti,qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: TI QSPI controller
8
9 maintainers:
10 - Kousik Sanagavarapu <five231003@gmail.com>
11
12 allOf:
13 - $ref: spi-controller.yaml#
14
15 properties:
16 compatible:
17 enum:
18 - ti,am4372-qspi
19 - ti,dra7xxx-qspi
20
21 reg:
22 items:
23 - description: base registers
24 - description: mapped memory
25
26 reg-names:
27 items:
28 - const: qspi_base
29 - const: qspi_mmap
30
31 clocks:
32 maxItems: 1
33
34 clock-names:
35 items:
36 - const: fck
37
38 interrupts:
39 maxItems: 1
40
41 num-cs:
42 minimum: 1
43 maximum: 4
44 default: 1
45
46 ti,hwmods:
47 description:
48 Name of the hwmod associated to the QSPI. This is for legacy
49 platforms only.
50 $ref: /schemas/types.yaml#/definitions/string
51 deprecated: true
52
53 syscon-chipselects:
54 description:
55 Handle to system control region containing QSPI chipselect register
56 and offset of that register.
57 $ref: /schemas/types.yaml#/definitions/phandle-array
58 items:
59 - items:
60 - description: phandle to system control register
61 - description: register offset
62
63 spi-max-frequency:
64 description: Maximum SPI clocking speed of the controller in Hz.
65 $ref: /schemas/types.yaml#/definitions/uint32
66
67 required:
68 - compatible
69 - reg
70 - reg-names
71 - clocks
72 - clock-names
73 - interrupts
74
75 unevaluatedProperties: false
76
77 examples:
78 - |
79 #include <dt-bindings/clock/dra7.h>
80 #include <dt-bindings/interrupt-controller/arm-gic.h>
81
82 spi@4b300000 {
83 compatible = "ti,dra7xxx-qspi";
84 reg = <0x4b300000 0x100>,
85 <0x5c000000 0x4000000>;
86 reg-names = "qspi_base", "qspi_mmap";
87 syscon-chipselects = <&scm_conf 0x558>;
88 #address-cells = <1>;
89 #size-cells = <0>;
90 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
91 clock-names = "fck";
92 num-cs = <4>;
93 spi-max-frequency = <48000000>;
94 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
95 };
96 ...
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