1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SPMI Controller (PMIC Arbiter)
8
9 maintainers:
10 - Stephen Boyd <sboyd@kernel.org>
11
12 description: |
13 The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
14 controller with wrapping arbitration logic to allow for multiple on-chip
15 devices to control a single SPMI master.
16
17 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
18 to slave devices.
19
20 allOf:
21 - $ref: spmi.yaml
22
23 properties:
24 compatible:
25 const: qcom,spmi-pmic-arb
26
27 reg:
28 oneOf:
29 - items: # V1
30 - description: core registers
31 - description: interrupt controller registers
32 - description: configuration registers
33 - items: # V2
34 - description: core registers
35 - description: tx-channel per virtual slave regosters
36 - description: rx-channel (called observer) per virtual slave registers
37 - description: interrupt controller registers
38 - description: configuration registers
39
40 reg-names:
41 oneOf:
42 - items:
43 - const: core
44 - const: intr
45 - const: cnfg
46 - items:
47 - const: core
48 - const: chnls
49 - const: obsrvr
50 - const: intr
51 - const: cnfg
52
53 interrupts:
54 maxItems: 1
55
56 interrupt-names:
57 const: periph_irq
58
59 interrupt-controller: true
60
61 '#address-cells': true
62
63 '#interrupt-cells':
64 const: 4
65 description: |
66 cell 1: slave ID for the requested interrupt (0-15)
67 cell 2: peripheral ID for requested interrupt (0-255)
68 cell 3: the requested peripheral interrupt (0-7)
69 cell 4: interrupt flags indicating level-sense information,
70 as defined in dt-bindings/interrupt-controller/irq.h
71
72 '#size-cells': true
73
74 qcom,ee:
75 $ref: /schemas/types.yaml#/definitions/uint32
76 minimum: 0
77 maximum: 5
78 description: >
79 indicates the active Execution Environment identifier
80
81 qcom,channel:
82 $ref: /schemas/types.yaml#/definitions/uint32
83 minimum: 0
84 maximum: 5
85 description: >
86 which of the PMIC Arb provided channels to use for accesses
87
88 qcom,bus-id:
89 $ref: /schemas/types.yaml#/definitions/uint32
90 minimum: 0
91 maximum: 1
92 description: >
93 SPMI bus instance. only applicable to PMIC arbiter version 7 and beyond.
94 Supported values, 0 = primary bus, 1 = secondary bus
95 deprecated: true
96
97 required:
98 - compatible
99 - reg-names
100 - qcom,ee
101 - qcom,channel
102
103 unevaluatedProperties: false
104
105 examples:
106 - |
107 spmi@fc4cf000 {
108 compatible = "qcom,spmi-pmic-arb";
109 reg-names = "core", "intr", "cnfg";
110 reg = <0xfc4cf000 0x1000>,
111 <0xfc4cb000 0x1000>,
112 <0xfc4ca000 0x1000>;
113
114 interrupt-names = "periph_irq";
115 interrupts = <0 190 0>;
116
117 qcom,ee = <0>;
118 qcom,channel = <0>;
119
120 #address-cells = <2>;
121 #size-cells = <0>;
122
123 interrupt-controller;
124 #interrupt-cells = <4>;
125
126 qcom,bus-id = <0>;
127 };
128
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