1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7)
8
9 maintainers:
10 - Stephen Boyd <sboyd@kernel.org>
11
12 description: |
13 The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI
14 controller with wrapping arbitration logic to allow for multiple on-chip
15 devices to control up to 2 SPMI separate buses.
16
17 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
18 to slave devices.
19
20 properties:
21 compatible:
22 const: qcom,x1e80100-spmi-pmic-arb
23
24 reg:
25 items:
26 - description: core registers
27 - description: tx-channel per virtual slave registers
28 - description: rx-channel (called observer) per virtual slave registers
29
30 reg-names:
31 items:
32 - const: core
33 - const: chnls
34 - const: obsrvr
35
36 ranges: true
37
38 '#address-cells':
39 const: 2
40
41 '#size-cells':
42 const: 2
43
44 qcom,ee:
45 $ref: /schemas/types.yaml#/definitions/uint32
46 minimum: 0
47 maximum: 5
48 description: >
49 indicates the active Execution Environment identifier
50
51 qcom,channel:
52 $ref: /schemas/types.yaml#/definitions/uint32
53 minimum: 0
54 maximum: 5
55 description: >
56 which of the PMIC Arb provided channels to use for accesses
57
58 patternProperties:
59 "^spmi@[a-f0-9]+$":
60 type: object
61 $ref: /schemas/spmi/spmi.yaml
62 unevaluatedProperties: false
63
64 properties:
65 reg:
66 items:
67 - description: configuration registers
68 - description: interrupt controller registers
69
70 reg-names:
71 items:
72 - const: cnfg
73 - const: intr
74
75 interrupts:
76 maxItems: 1
77
78 interrupt-names:
79 const: periph_irq
80
81 interrupt-controller: true
82
83 '#interrupt-cells':
84 const: 4
85 description: |
86 cell 1: slave ID for the requested interrupt (0-15)
87 cell 2: peripheral ID for requested interrupt (0-255)
88 cell 3: the requested peripheral interrupt (0-7)
89 cell 4: interrupt flags indicating level-sense information,
90 as defined in dt-bindings/interrupt-controller/irq.h
91
92 required:
93 - compatible
94 - reg-names
95 - qcom,ee
96 - qcom,channel
97
98 additionalProperties: false
99
100 examples:
101 - |
102 #include <dt-bindings/interrupt-controller/arm-gic.h>
103
104 soc {
105 #address-cells = <2>;
106 #size-cells = <2>;
107
108 spmi: arbiter@c400000 {
109 compatible = "qcom,x1e80100-spmi-pmic-arb";
110 reg = <0 0x0c400000 0 0x3000>,
111 <0 0x0c500000 0 0x4000000>,
112 <0 0x0c440000 0 0x80000>;
113 reg-names = "core", "chnls", "obsrvr";
114
115 qcom,ee = <0>;
116 qcom,channel = <0>;
117
118 #address-cells = <2>;
119 #size-cells = <2>;
120 ranges;
121
122 spmi_bus0: spmi@c42d000 {
123 reg = <0 0x0c42d000 0 0x4000>,
124 <0 0x0c4c0000 0 0x10000>;
125 reg-names = "cnfg", "intr";
126
127 interrupt-names = "periph_irq";
128 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
129 interrupt-controller;
130 #interrupt-cells = <4>;
131
132 #address-cells = <2>;
133 #size-cells = <0>;
134 };
135 };
136 };
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