1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2020 Linaro Ltd.
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7
8 title: Thermal idle cooling device
9
10 maintainers:
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
12
13 description: |
14 The thermal idle cooling device allows the system to passively
15 mitigate the temperature on the device by injecting idle cycles,
16 forcing it to cool down.
17
18 This binding describes the thermal idle node.
19
20 properties:
21 $nodename:
22 const: thermal-idle
23 description: |
24 A thermal-idle node describes the idle cooling device properties to
25 cool down efficiently the attached thermal zone.
26
27 '#cooling-cells':
28 const: 2
29 description: |
30 Must be 2, in order to specify minimum and maximum cooling state used in
31 the cooling-maps reference. The first cell is the minimum cooling state
32 and the second cell is the maximum cooling state requested.
33
34 duration-us:
35 description: |
36 The idle duration in microsecond the device should cool down.
37
38 exit-latency-us:
39 description: |
40 The exit latency constraint in microsecond for the injected idle state
41 for the device. It is the latency constraint to apply when selecting an
42 idle state from among all the present ones.
43
44 required:
45 - '#cooling-cells'
46
47 additionalProperties: false
48
49 examples:
50 - |
51 /{
52 #include <dt-bindings/thermal/thermal.h>
53
54 compatible = "foo";
55 model = "foo";
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 // Example: Combining idle cooling device on big CPUs with cpufreq cooling device
60 cpus {
61 #address-cells = <2>;
62 #size-cells = <0>;
63
64 /* ... */
65
66 cpu_b0: cpu@100 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a72";
69 reg = <0x0 0x100>;
70 enable-method = "psci";
71 capacity-dmips-mhz = <1024>;
72 dynamic-power-coefficient = <436>;
73 #cooling-cells = <2>; /* min followed by max */
74 cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
75 cpu_b0_therm: thermal-idle {
76 #cooling-cells = <2>;
77 duration-us = <10000>;
78 exit-latency-us = <500>;
79 };
80 };
81
82 cpu_b1: cpu@101 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a72";
85 reg = <0x0 0x101>;
86 enable-method = "psci";
87 capacity-dmips-mhz = <1024>;
88 dynamic-power-coefficient = <436>;
89 #cooling-cells = <2>; /* min followed by max */
90 cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
91 cpu_b1_therm: thermal-idle {
92 #cooling-cells = <2>;
93 duration-us = <10000>;
94 exit-latency-us = <500>;
95 };
96 };
97
98 /* ... */
99
100 };
101
102 /* ... */
103
104 thermal_zones {
105 cpu_thermal: cpu {
106 polling-delay-passive = <100>;
107 polling-delay = <1000>;
108
109 /* ... */
110
111 trips {
112 cpu_alert0: cpu_alert0 {
113 temperature = <65000>;
114 hysteresis = <2000>;
115 type = "passive";
116 };
117
118 cpu_alert1: cpu_alert1 {
119 temperature = <70000>;
120 hysteresis = <2000>;
121 type = "passive";
122 };
123
124 cpu_alert2: cpu_alert2 {
125 temperature = <75000>;
126 hysteresis = <2000>;
127 type = "passive";
128 };
129
130 cpu_crit: cpu_crit {
131 temperature = <95000>;
132 hysteresis = <2000>;
133 type = "critical";
134 };
135 };
136
137 cooling-maps {
138 map0 {
139 trip = <&cpu_alert1>;
140 cooling-device = <&cpu_b0_therm 0 15 >,
141 <&cpu_b1_therm 0 15>;
142 };
143
144 map1 {
145 trip = <&cpu_alert2>;
146 cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
147 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
148 };
149 };
150 };
151 };
152 };
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