1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Aspeed watchdog timer controllers
8
9 maintainers:
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
11
12 properties:
13 compatible:
14 enum:
15 - aspeed,ast2400-wdt
16 - aspeed,ast2500-wdt
17 - aspeed,ast2600-wdt
18
19 reg:
20 maxItems: 1
21
22 clocks:
23 maxItems: 1
24 description: >
25 The clock used to drive the watchdog counter. From the AST2500 no source
26 other than the 1MHz clock can be selected, so the clocks property is
27 optional.
28
29 aspeed,reset-type:
30 $ref: /schemas/types.yaml#/definitions/string
31 enum:
32 - cpu
33 - soc
34 - system
35 - none
36 default: system
37 description: >
38 The watchdog can be programmed to generate one of three different types of
39 reset when a timeout occcurs.
40
41 Specifying 'cpu' will only reset the processor on a timeout event.
42
43 Specifying 'soc' will reset a configurable subset of the SoC's controllers
44 on a timeout event. Controllers critical to the SoC's operation may remain
45 untouched. The set of SoC controllers to reset may be specified via the
46 aspeed,reset-mask property if the node has the aspeed,ast2500-wdt or
47 aspeed,ast2600-wdt compatible.
48
49 Specifying 'system' will reset all controllers on a timeout event, as if
50 EXTRST had been asserted.
51
52 Specifying 'none' will cause the timeout event to have no reset effect.
53 Another watchdog engine on the chip must be used for chip reset operations.
54
55 aspeed,alt-boot:
56 $ref: /schemas/types.yaml#/definitions/flag
57 description: >
58 Direct the watchdog to configure the SoC to boot from the alternative boot
59 region if a timeout occurs.
60
61 aspeed,external-signal:
62 $ref: /schemas/types.yaml#/definitions/flag
63 description: >
64 Assert the timeout event on an external signal pin associated with the
65 watchdog controller instance. The pin must be muxed appropriately.
66
67 aspeed,ext-pulse-duration:
68 $ref: /schemas/types.yaml#/definitions/uint32
69 description: >
70 The duration, in microseconds, of the pulse emitted on the external signal
71 pin.
72
73 aspeed,ext-push-pull:
74 $ref: /schemas/types.yaml#/definitions/flag
75 description: >
76 If aspeed,external-signal is specified in the node, set the external
77 signal pin's drive type to push-pull. If aspeed,ext-push-pull is not
78 specified then the pin is configured as open-drain.
79
80 aspeed,ext-active-high:
81 $ref: /schemas/types.yaml#/definitions/flag
82 description: >
83 If both aspeed,external-signal and aspeed,ext-push-pull are specified in
84 the node, set the pulse polarity to active-high. If aspeed,ext-active-high
85 is not specified then the pin is configured as active-low.
86
87 aspeed,reset-mask:
88 $ref: /schemas/types.yaml#/definitions/uint32-array
89 minItems: 1
90 maxItems: 2
91 description: >
92 A bitmask indicating which peripherals will be reset if the watchdog
93 timer expires. On AST2500 SoCs this should be a single word defined using
94 the AST2500_WDT_RESET_* macros; on AST2600 SoCs this should be a two-word
95 array with the first word defined using the AST2600_WDT_RESET1_* macros,
96 and the second word defined using the AST2600_WDT_RESET2_* macros.
97
98 required:
99 - compatible
100 - reg
101
102 allOf:
103 - if:
104 anyOf:
105 - required:
106 - aspeed,ext-push-pull
107 - required:
108 - aspeed,ext-active-high
109 - required:
110 - aspeed,reset-mask
111 then:
112 properties:
113 compatible:
114 enum:
115 - aspeed,ast2500-wdt
116 - aspeed,ast2600-wdt
117 - if:
118 required:
119 - aspeed,ext-active-high
120 then:
121 required:
122 - aspeed,ext-push-pull
123
124 additionalProperties: false
125
126 examples:
127 - |
128 watchdog@1e785000 {
129 compatible = "aspeed,ast2400-wdt";
130 reg = <0x1e785000 0x1c>;
131 aspeed,reset-type = "system";
132 aspeed,external-signal;
133 };
134 - |
135 #include <dt-bindings/watchdog/aspeed-wdt.h>
136 watchdog@1e785040 {
137 compatible = "aspeed,ast2600-wdt";
138 reg = <0x1e785040 0x40>;
139 aspeed,reset-type = "soc";
140 aspeed,reset-mask = <AST2600_WDT_RESET1_DEFAULT
141 (AST2600_WDT_RESET2_DEFAULT & ~AST2600_WDT_RESET2_LPC)>;
142 };
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