1 .. SPDX-License-Identifier: GPL-2.0 2 .. include:: <isonum.txt> 3 4 =========================================== 5 Compute Express Link Subsystem Maturity Map 6 =========================================== 7 8 The Linux CXL subsystem tracks the dynamic `CXL specification 9 <https://computeexpresslink.org/cxl-specification-landing-page>`_ that 10 continues to respond to new use cases with new features, capability 11 updates and fixes. At any given point some aspects of the subsystem are 12 more mature than others. While the periodic pull requests summarize the 13 `work being incorporated each merge window 14 <https://lore.kernel.org/linux-cxl/?q=s%3APULL+s%3ACXL+tc%3Atorvalds+NOT+s%3ARe>`_, 15 those do not always convey progress relative to a starting point and a 16 future end goal. 17 18 What follows is a coarse breakdown of the subsystem's major 19 responsibilities along with a maturity score. The expectation is that 20 the change-history of this document provides an overview summary of the 21 subsystem maturation over time. 22 23 The maturity scores are: 24 25 - [3] Mature: Work in this area is complete and no changes on the horizon. 26 Note that this score can regress from one kernel release to the next 27 based on new test results or end user reports. 28 29 - [2] Stabilizing: Major functionality operational, common cases are 30 mature, but known corner cases are still a work in progress. 31 32 - [1] Initial: Capability that has exited the Proof of Concept phase, but 33 may still have significant gaps to close and fixes to apply as real 34 world testing occurs. 35 36 - [0] Known gap: Feature is on a medium to long term horizon to 37 implement. If the specification has a feature that does not even have 38 a '0' score in this document, there is a good chance that no one in 39 the linux-cxl@vger.kernel.org community has started to look at it. 40 41 - X: Out of scope for kernel enabling, or kernel enabling not required 42 43 Feature and Capabilities 44 ======================== 45 46 Enumeration / Provisioning 47 -------------------------- 48 All of the fundamental enumeration an object model of the subsystem is 49 in place, but there are several corner cases that are pending closure. 50 51 52 * [2] CXL Window Enumeration 53 54 * [0] :ref:`Extended-linear memory-side cache <extended-linear>` 55 * [0] Low Memory-hole 56 * [0] Hetero-interleave 57 58 * [2] Switch Enumeration 59 60 * [0] CXL register enumeration link-up dependency 61 62 * [2] HDM Decoder Configuration 63 64 * [0] Decoder target and granularity constraints 65 66 * [2] Performance enumeration 67 68 * [3] Endpoint CDAT 69 * [3] Switch CDAT 70 * [1] CDAT to Core-mm integration 71 72 * [1] x86 73 * [0] Arm64 74 * [0] All other arch. 75 76 * [0] Shared link 77 78 * [2] Hotplug 79 (see CXL Window Enumeration) 80 81 * [0] Handle Soft Reserved conflicts 82 83 * [0] :ref:`RCH link status <rch-link-status>` 84 * [0] Fabrics / G-FAM (chapter 7) 85 * [0] Global Access Endpoint 86 87 88 RAS 89 --- 90 In many ways CXL can be seen as a standardization of what would normally 91 be handled by custom EDAC drivers. The open development here is 92 mainly caused by the enumeration corner cases above. 93 94 * [3] Component events (OS) 95 * [2] Component events (FFM) 96 * [1] Endpoint protocol errors (OS) 97 * [1] Endpoint protocol errors (FFM) 98 * [0] Switch protocol errors (OS) 99 * [1] Switch protocol errors (FFM) 100 * [2] DPA->HPA Address translation 101 102 * [1] XOR Interleave translation 103 (see CXL Window Enumeration) 104 105 * [1] Memory Failure coordination 106 * [0] Scrub control 107 * [2] ACPI error injection EINJ 108 109 * [0] EINJ v2 110 * [X] Compliance DOE 111 112 * [2] Native error injection 113 * [3] RCH error handling 114 * [1] VH error handling 115 * [0] PPR 116 * [0] Sparing 117 * [0] Device built in test 118 119 120 Mailbox commands 121 ---------------- 122 123 * [3] Firmware update 124 * [3] Health / Alerts 125 * [1] :ref:`Background commands <background-commands>` 126 * [3] Sanitization 127 * [3] Security commands 128 * [3] RAW Command Debug Passthrough 129 * [0] CEL-only-validation Passthrough 130 * [0] Switch CCI 131 * [3] Timestamp 132 * [1] PMEM labels 133 * [0] PMEM GPF / Dirty Shutdown 134 * [0] Scan Media 135 136 PMU 137 --- 138 * [1] Type 3 PMU 139 * [0] Switch USP/ DSP, Root Port 140 141 Security 142 -------- 143 144 * [X] CXL Trusted Execution Environment Security Protocol (TSP) 145 * [X] CXL IDE (subsumed by TSP) 146 147 Memory-pooling 148 -------------- 149 150 * [1] Hotplug of LDs (via PCI hotplug) 151 * [0] Dynamic Capacity Device (DCD) Support 152 153 Multi-host sharing 154 ------------------ 155 156 * [0] Hardware coherent shared memory 157 * [0] Software managed coherency shared memory 158 159 Multi-host memory 160 ----------------- 161 162 * [0] Dynamic Capacity Device Support 163 * [0] Sharing 164 165 Accelerator 166 ----------- 167 168 * [0] Accelerator memory enumeration HDM-D (CXL 1.1/2.0 Type-2) 169 * [0] Accelerator memory enumeration HDM-DB (CXL 3.0 Type-2) 170 * [0] CXL.cache 68b (CXL 2.0) 171 * [0] CXL.cache 256b Cache IDs (CXL 3.0) 172 173 User Flow Support 174 ----------------- 175 176 * [0] HPA->DPA Address translation (need xormaps export solution) 177 178 Details 179 ======= 180 181 .. _extended-linear: 182 183 * **Extended-linear memory-side cache**: An HMAT proposal to enumerate the presence of a 184 memory-side cache where the cache capacity extends the SRAT address 185 range capacity. `See the ECN 186 <https://lore.kernel.org/linux-cxl/6650e4f835a0e_195e294a8@dwillia2-mobl3.amr.corp.intel.com.notmuch/">https://lore.kernel.org/linux-cxl/6650e4f835a0e_195e294a8@dwillia2-mobl3.amr.corp.intel.com.notmuch/>`_ 187 for more details: 188 189 .. _rch-link-status: 190 191 * **RCH Link Status**: RCH (Restricted CXL Host) topologies, end up 192 hiding some standard registers like PCIe Link Status / Capabilities in 193 the CXL RCRB (Root Complex Register Block). 194 195 .. _background-commands: 196 197 * **Background commands**: The CXL background command mechanism is 198 awkward as the single slot is monopolized potentially indefinitely by 199 various commands. A `cancel on conflict 200 <http://lore.kernel.org/r/66035c2e8ba17_770232948b@dwillia2-xfh.jf.intel.com.notmuch">http://lore.kernel.org/r/66035c2e8ba17_770232948b@dwillia2-xfh.jf.intel.com.notmuch>`_ 201 facility is needed to make sure the kernel can ensure forward progress 202 of priority commands.
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