1 =====================================
2 MTD NAND Driver Programming Interface
3 =====================================
4
5 :Author: Thomas Gleixner
6
7 Introduction
8 ============
9
10 The generic NAND driver supports almost all NAND and AG-AND based chips
11 and connects them to the Memory Technology Devices (MTD) subsystem of
12 the Linux Kernel.
13
14 This documentation is provided for developers who want to implement
15 board drivers or filesystem drivers suitable for NAND devices.
16
17 Known Bugs And Assumptions
18 ==========================
19
20 None.
21
22 Documentation hints
23 ===================
24
25 The function and structure docs are autogenerated. Each function and
26 struct member has a short description which is marked with an [XXX]
27 identifier. The following chapters explain the meaning of those
28 identifiers.
29
30 Function identifiers [XXX]
31 --------------------------
32
33 The functions are marked with [XXX] identifiers in the short comment.
34 The identifiers explain the usage and scope of the functions. Following
35 identifiers are used:
36
37 - [MTD Interface]
38
39 These functions provide the interface to the MTD kernel API. They are
40 not replaceable and provide functionality which is complete hardware
41 independent.
42
43 - [NAND Interface]
44
45 These functions are exported and provide the interface to the NAND
46 kernel API.
47
48 - [GENERIC]
49
50 Generic functions are not replaceable and provide functionality which
51 is complete hardware independent.
52
53 - [DEFAULT]
54
55 Default functions provide hardware related functionality which is
56 suitable for most of the implementations. These functions can be
57 replaced by the board driver if necessary. Those functions are called
58 via pointers in the NAND chip description structure. The board driver
59 can set the functions which should be replaced by board dependent
60 functions before calling nand_scan(). If the function pointer is
61 NULL on entry to nand_scan() then the pointer is set to the default
62 function which is suitable for the detected chip type.
63
64 Struct member identifiers [XXX]
65 -------------------------------
66
67 The struct members are marked with [XXX] identifiers in the comment. The
68 identifiers explain the usage and scope of the members. Following
69 identifiers are used:
70
71 - [INTERN]
72
73 These members are for NAND driver internal use only and must not be
74 modified. Most of these values are calculated from the chip geometry
75 information which is evaluated during nand_scan().
76
77 - [REPLACEABLE]
78
79 Replaceable members hold hardware related functions which can be
80 provided by the board driver. The board driver can set the functions
81 which should be replaced by board dependent functions before calling
82 nand_scan(). If the function pointer is NULL on entry to
83 nand_scan() then the pointer is set to the default function which is
84 suitable for the detected chip type.
85
86 - [BOARDSPECIFIC]
87
88 Board specific members hold hardware related information which must
89 be provided by the board driver. The board driver must set the
90 function pointers and datafields before calling nand_scan().
91
92 - [OPTIONAL]
93
94 Optional members can hold information relevant for the board driver.
95 The generic NAND driver code does not use this information.
96
97 Basic board driver
98 ==================
99
100 For most boards it will be sufficient to provide just the basic
101 functions and fill out some really board dependent members in the nand
102 chip description structure.
103
104 Basic defines
105 -------------
106
107 At least you have to provide a nand_chip structure and a storage for
108 the ioremap'ed chip address. You can allocate the nand_chip structure
109 using kmalloc or you can allocate it statically. The NAND chip structure
110 embeds an mtd structure which will be registered to the MTD subsystem.
111 You can extract a pointer to the mtd structure from a nand_chip pointer
112 using the nand_to_mtd() helper.
113
114 Kmalloc based example
115
116 ::
117
118 static struct mtd_info *board_mtd;
119 static void __iomem *baseaddr;
120
121
122 Static example
123
124 ::
125
126 static struct nand_chip board_chip;
127 static void __iomem *baseaddr;
128
129
130 Partition defines
131 -----------------
132
133 If you want to divide your device into partitions, then define a
134 partitioning scheme suitable to your board.
135
136 ::
137
138 #define NUM_PARTITIONS 2
139 static struct mtd_partition partition_info[] = {
140 { .name = "Flash partition 1",
141 .offset = 0,
142 .size = 8 * 1024 * 1024 },
143 { .name = "Flash partition 2",
144 .offset = MTDPART_OFS_NEXT,
145 .size = MTDPART_SIZ_FULL },
146 };
147
148
149 Hardware control function
150 -------------------------
151
152 The hardware control function provides access to the control pins of the
153 NAND chip(s). The access can be done by GPIO pins or by address lines.
154 If you use address lines, make sure that the timing requirements are
155 met.
156
157 *GPIO based example*
158
159 ::
160
161 static void board_hwcontrol(struct mtd_info *mtd, int cmd)
162 {
163 switch(cmd){
164 case NAND_CTL_SETCLE: /* Set CLE pin high */ break;
165 case NAND_CTL_CLRCLE: /* Set CLE pin low */ break;
166 case NAND_CTL_SETALE: /* Set ALE pin high */ break;
167 case NAND_CTL_CLRALE: /* Set ALE pin low */ break;
168 case NAND_CTL_SETNCE: /* Set nCE pin low */ break;
169 case NAND_CTL_CLRNCE: /* Set nCE pin high */ break;
170 }
171 }
172
173
174 *Address lines based example.* It's assumed that the nCE pin is driven
175 by a chip select decoder.
176
177 ::
178
179 static void board_hwcontrol(struct mtd_info *mtd, int cmd)
180 {
181 struct nand_chip *this = mtd_to_nand(mtd);
182 switch(cmd){
183 case NAND_CTL_SETCLE: this->legacy.IO_ADDR_W |= CLE_ADRR_BIT; break;
184 case NAND_CTL_CLRCLE: this->legacy.IO_ADDR_W &= ~CLE_ADRR_BIT; break;
185 case NAND_CTL_SETALE: this->legacy.IO_ADDR_W |= ALE_ADRR_BIT; break;
186 case NAND_CTL_CLRALE: this->legacy.IO_ADDR_W &= ~ALE_ADRR_BIT; break;
187 }
188 }
189
190
191 Device ready function
192 ---------------------
193
194 If the hardware interface has the ready busy pin of the NAND chip
195 connected to a GPIO or other accessible I/O pin, this function is used
196 to read back the state of the pin. The function has no arguments and
197 should return 0, if the device is busy (R/B pin is low) and 1, if the
198 device is ready (R/B pin is high). If the hardware interface does not
199 give access to the ready busy pin, then the function must not be defined
200 and the function pointer this->legacy.dev_ready is set to NULL.
201
202 Init function
203 -------------
204
205 The init function allocates memory and sets up all the board specific
206 parameters and function pointers. When everything is set up nand_scan()
207 is called. This function tries to detect and identify then chip. If a
208 chip is found all the internal data fields are initialized accordingly.
209 The structure(s) have to be zeroed out first and then filled with the
210 necessary information about the device.
211
212 ::
213
214 static int __init board_init (void)
215 {
216 struct nand_chip *this;
217 int err = 0;
218
219 /* Allocate memory for MTD device structure and private data */
220 this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
221 if (!this) {
222 printk ("Unable to allocate NAND MTD device structure.\n");
223 err = -ENOMEM;
224 goto out;
225 }
226
227 board_mtd = nand_to_mtd(this);
228
229 /* map physical address */
230 baseaddr = ioremap(CHIP_PHYSICAL_ADDRESS, 1024);
231 if (!baseaddr) {
232 printk("Ioremap to access NAND chip failed\n");
233 err = -EIO;
234 goto out_mtd;
235 }
236
237 /* Set address of NAND IO lines */
238 this->legacy.IO_ADDR_R = baseaddr;
239 this->legacy.IO_ADDR_W = baseaddr;
240 /* Reference hardware control function */
241 this->hwcontrol = board_hwcontrol;
242 /* Set command delay time, see datasheet for correct value */
243 this->legacy.chip_delay = CHIP_DEPENDEND_COMMAND_DELAY;
244 /* Assign the device ready function, if available */
245 this->legacy.dev_ready = board_dev_ready;
246 this->eccmode = NAND_ECC_SOFT;
247
248 /* Scan to find existence of the device */
249 if (nand_scan (this, 1)) {
250 err = -ENXIO;
251 goto out_ior;
252 }
253
254 add_mtd_partitions(board_mtd, partition_info, NUM_PARTITIONS);
255 goto out;
256
257 out_ior:
258 iounmap(baseaddr);
259 out_mtd:
260 kfree (this);
261 out:
262 return err;
263 }
264 module_init(board_init);
265
266
267 Exit function
268 -------------
269
270 The exit function is only necessary if the driver is compiled as a
271 module. It releases all resources which are held by the chip driver and
272 unregisters the partitions in the MTD layer.
273
274 ::
275
276 #ifdef MODULE
277 static void __exit board_cleanup (void)
278 {
279 /* Unregister device */
280 WARN_ON(mtd_device_unregister(board_mtd));
281 /* Release resources */
282 nand_cleanup(mtd_to_nand(board_mtd));
283
284 /* unmap physical address */
285 iounmap(baseaddr);
286
287 /* Free the MTD device structure */
288 kfree (mtd_to_nand(board_mtd));
289 }
290 module_exit(board_cleanup);
291 #endif
292
293
294 Advanced board driver functions
295 ===============================
296
297 This chapter describes the advanced functionality of the NAND driver.
298 For a list of functions which can be overridden by the board driver see
299 the documentation of the nand_chip structure.
300
301 Multiple chip control
302 ---------------------
303
304 The nand driver can control chip arrays. Therefore the board driver must
305 provide an own select_chip function. This function must (de)select the
306 requested chip. The function pointer in the nand_chip structure must be
307 set before calling nand_scan(). The maxchip parameter of nand_scan()
308 defines the maximum number of chips to scan for. Make sure that the
309 select_chip function can handle the requested number of chips.
310
311 The nand driver concatenates the chips to one virtual chip and provides
312 this virtual chip to the MTD layer.
313
314 *Note: The driver can only handle linear chip arrays of equally sized
315 chips. There is no support for parallel arrays which extend the
316 buswidth.*
317
318 *GPIO based example*
319
320 ::
321
322 static void board_select_chip (struct mtd_info *mtd, int chip)
323 {
324 /* Deselect all chips, set all nCE pins high */
325 GPIO(BOARD_NAND_NCE) |= 0xff;
326 if (chip >= 0)
327 GPIO(BOARD_NAND_NCE) &= ~ (1 << chip);
328 }
329
330
331 *Address lines based example.* Its assumed that the nCE pins are
332 connected to an address decoder.
333
334 ::
335
336 static void board_select_chip (struct mtd_info *mtd, int chip)
337 {
338 struct nand_chip *this = mtd_to_nand(mtd);
339
340 /* Deselect all chips */
341 this->legacy.IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK;
342 this->legacy.IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK;
343 switch (chip) {
344 case 0:
345 this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0;
346 this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0;
347 break;
348 ....
349 case n:
350 this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn;
351 this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn;
352 break;
353 }
354 }
355
356
357 Hardware ECC support
358 --------------------
359
360 Functions and constants
361 ~~~~~~~~~~~~~~~~~~~~~~~
362
363 The nand driver supports three different types of hardware ECC.
364
365 - NAND_ECC_HW3_256
366
367 Hardware ECC generator providing 3 bytes ECC per 256 byte.
368
369 - NAND_ECC_HW3_512
370
371 Hardware ECC generator providing 3 bytes ECC per 512 byte.
372
373 - NAND_ECC_HW6_512
374
375 Hardware ECC generator providing 6 bytes ECC per 512 byte.
376
377 - NAND_ECC_HW8_512
378
379 Hardware ECC generator providing 8 bytes ECC per 512 byte.
380
381 If your hardware generator has a different functionality add it at the
382 appropriate place in nand_base.c
383
384 The board driver must provide following functions:
385
386 - enable_hwecc
387
388 This function is called before reading / writing to the chip. Reset
389 or initialize the hardware generator in this function. The function
390 is called with an argument which let you distinguish between read and
391 write operations.
392
393 - calculate_ecc
394
395 This function is called after read / write from / to the chip.
396 Transfer the ECC from the hardware to the buffer. If the option
397 NAND_HWECC_SYNDROME is set then the function is only called on
398 write. See below.
399
400 - correct_data
401
402 In case of an ECC error this function is called for error detection
403 and correction. Return 1 respectively 2 in case the error can be
404 corrected. If the error is not correctable return -1. If your
405 hardware generator matches the default algorithm of the nand_ecc
406 software generator then use the correction function provided by
407 nand_ecc instead of implementing duplicated code.
408
409 Hardware ECC with syndrome calculation
410 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
411
412 Many hardware ECC implementations provide Reed-Solomon codes and
413 calculate an error syndrome on read. The syndrome must be converted to a
414 standard Reed-Solomon syndrome before calling the error correction code
415 in the generic Reed-Solomon library.
416
417 The ECC bytes must be placed immediately after the data bytes in order
418 to make the syndrome generator work. This is contrary to the usual
419 layout used by software ECC. The separation of data and out of band area
420 is not longer possible. The nand driver code handles this layout and the
421 remaining free bytes in the oob area are managed by the autoplacement
422 code. Provide a matching oob-layout in this case. See rts_from4.c and
423 diskonchip.c for implementation reference. In those cases we must also
424 use bad block tables on FLASH, because the ECC layout is interfering
425 with the bad block marker positions. See bad block table support for
426 details.
427
428 Bad block table support
429 -----------------------
430
431 Most NAND chips mark the bad blocks at a defined position in the spare
432 area. Those blocks must not be erased under any circumstances as the bad
433 block information would be lost. It is possible to check the bad block
434 mark each time when the blocks are accessed by reading the spare area of
435 the first page in the block. This is time consuming so a bad block table
436 is used.
437
438 The nand driver supports various types of bad block tables.
439
440 - Per device
441
442 The bad block table contains all bad block information of the device
443 which can consist of multiple chips.
444
445 - Per chip
446
447 A bad block table is used per chip and contains the bad block
448 information for this particular chip.
449
450 - Fixed offset
451
452 The bad block table is located at a fixed offset in the chip
453 (device). This applies to various DiskOnChip devices.
454
455 - Automatic placed
456
457 The bad block table is automatically placed and detected either at
458 the end or at the beginning of a chip (device)
459
460 - Mirrored tables
461
462 The bad block table is mirrored on the chip (device) to allow updates
463 of the bad block table without data loss.
464
465 nand_scan() calls the function nand_default_bbt().
466 nand_default_bbt() selects appropriate default bad block table
467 descriptors depending on the chip information which was retrieved by
468 nand_scan().
469
470 The standard policy is scanning the device for bad blocks and build a
471 ram based bad block table which allows faster access than always
472 checking the bad block information on the flash chip itself.
473
474 Flash based tables
475 ~~~~~~~~~~~~~~~~~~
476
477 It may be desired or necessary to keep a bad block table in FLASH. For
478 AG-AND chips this is mandatory, as they have no factory marked bad
479 blocks. They have factory marked good blocks. The marker pattern is
480 erased when the block is erased to be reused. So in case of powerloss
481 before writing the pattern back to the chip this block would be lost and
482 added to the bad blocks. Therefore we scan the chip(s) when we detect
483 them the first time for good blocks and store this information in a bad
484 block table before erasing any of the blocks.
485
486 The blocks in which the tables are stored are protected against
487 accidental access by marking them bad in the memory bad block table. The
488 bad block table management functions are allowed to circumvent this
489 protection.
490
491 The simplest way to activate the FLASH based bad block table support is
492 to set the option NAND_BBT_USE_FLASH in the bbt_option field of the
493 nand chip structure before calling nand_scan(). For AG-AND chips is
494 this done by default. This activates the default FLASH based bad block
495 table functionality of the NAND driver. The default bad block table
496 options are
497
498 - Store bad block table per chip
499
500 - Use 2 bits per block
501
502 - Automatic placement at the end of the chip
503
504 - Use mirrored tables with version numbers
505
506 - Reserve 4 blocks at the end of the chip
507
508 User defined tables
509 ~~~~~~~~~~~~~~~~~~~
510
511 User defined tables are created by filling out a nand_bbt_descr
512 structure and storing the pointer in the nand_chip structure member
513 bbt_td before calling nand_scan(). If a mirror table is necessary a
514 second structure must be created and a pointer to this structure must be
515 stored in bbt_md inside the nand_chip structure. If the bbt_md member
516 is set to NULL then only the main table is used and no scan for the
517 mirrored table is performed.
518
519 The most important field in the nand_bbt_descr structure is the
520 options field. The options define most of the table properties. Use the
521 predefined constants from rawnand.h to define the options.
522
523 - Number of bits per block
524
525 The supported number of bits is 1, 2, 4, 8.
526
527 - Table per chip
528
529 Setting the constant NAND_BBT_PERCHIP selects that a bad block
530 table is managed for each chip in a chip array. If this option is not
531 set then a per device bad block table is used.
532
533 - Table location is absolute
534
535 Use the option constant NAND_BBT_ABSPAGE and define the absolute
536 page number where the bad block table starts in the field pages. If
537 you have selected bad block tables per chip and you have a multi chip
538 array then the start page must be given for each chip in the chip
539 array. Note: there is no scan for a table ident pattern performed, so
540 the fields pattern, veroffs, offs, len can be left uninitialized
541
542 - Table location is automatically detected
543
544 The table can either be located in the first or the last good blocks
545 of the chip (device). Set NAND_BBT_LASTBLOCK to place the bad block
546 table at the end of the chip (device). The bad block tables are
547 marked and identified by a pattern which is stored in the spare area
548 of the first page in the block which holds the bad block table. Store
549 a pointer to the pattern in the pattern field. Further the length of
550 the pattern has to be stored in len and the offset in the spare area
551 must be given in the offs member of the nand_bbt_descr structure.
552 For mirrored bad block tables different patterns are mandatory.
553
554 - Table creation
555
556 Set the option NAND_BBT_CREATE to enable the table creation if no
557 table can be found during the scan. Usually this is done only once if
558 a new chip is found.
559
560 - Table write support
561
562 Set the option NAND_BBT_WRITE to enable the table write support.
563 This allows the update of the bad block table(s) in case a block has
564 to be marked bad due to wear. The MTD interface function
565 block_markbad is calling the update function of the bad block table.
566 If the write support is enabled then the table is updated on FLASH.
567
568 Note: Write support should only be enabled for mirrored tables with
569 version control.
570
571 - Table version control
572
573 Set the option NAND_BBT_VERSION to enable the table version
574 control. It's highly recommended to enable this for mirrored tables
575 with write support. It makes sure that the risk of losing the bad
576 block table information is reduced to the loss of the information
577 about the one worn out block which should be marked bad. The version
578 is stored in 4 consecutive bytes in the spare area of the device. The
579 position of the version number is defined by the member veroffs in
580 the bad block table descriptor.
581
582 - Save block contents on write
583
584 In case that the block which holds the bad block table does contain
585 other useful information, set the option NAND_BBT_SAVECONTENT. When
586 the bad block table is written then the whole block is read the bad
587 block table is updated and the block is erased and everything is
588 written back. If this option is not set only the bad block table is
589 written and everything else in the block is ignored and erased.
590
591 - Number of reserved blocks
592
593 For automatic placement some blocks must be reserved for bad block
594 table storage. The number of reserved blocks is defined in the
595 maxblocks member of the bad block table description structure.
596 Reserving 4 blocks for mirrored tables should be a reasonable number.
597 This also limits the number of blocks which are scanned for the bad
598 block table ident pattern.
599
600 Spare area (auto)placement
601 --------------------------
602
603 The nand driver implements different possibilities for placement of
604 filesystem data in the spare area,
605
606 - Placement defined by fs driver
607
608 - Automatic placement
609
610 The default placement function is automatic placement. The nand driver
611 has built in default placement schemes for the various chiptypes. If due
612 to hardware ECC functionality the default placement does not fit then
613 the board driver can provide a own placement scheme.
614
615 File system drivers can provide a own placement scheme which is used
616 instead of the default placement scheme.
617
618 Placement schemes are defined by a nand_oobinfo structure
619
620 ::
621
622 struct nand_oobinfo {
623 int useecc;
624 int eccbytes;
625 int eccpos[24];
626 int oobfree[8][2];
627 };
628
629
630 - useecc
631
632 The useecc member controls the ecc and placement function. The header
633 file include/mtd/mtd-abi.h contains constants to select ecc and
634 placement. MTD_NANDECC_OFF switches off the ecc complete. This is
635 not recommended and available for testing and diagnosis only.
636 MTD_NANDECC_PLACE selects caller defined placement,
637 MTD_NANDECC_AUTOPLACE selects automatic placement.
638
639 - eccbytes
640
641 The eccbytes member defines the number of ecc bytes per page.
642
643 - eccpos
644
645 The eccpos array holds the byte offsets in the spare area where the
646 ecc codes are placed.
647
648 - oobfree
649
650 The oobfree array defines the areas in the spare area which can be
651 used for automatic placement. The information is given in the format
652 {offset, size}. offset defines the start of the usable area, size the
653 length in bytes. More than one area can be defined. The list is
654 terminated by an {0, 0} entry.
655
656 Placement defined by fs driver
657 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
658
659 The calling function provides a pointer to a nand_oobinfo structure
660 which defines the ecc placement. For writes the caller must provide a
661 spare area buffer along with the data buffer. The spare area buffer size
662 is (number of pages) \* (size of spare area). For reads the buffer size
663 is (number of pages) \* ((size of spare area) + (number of ecc steps per
664 page) \* sizeof (int)). The driver stores the result of the ecc check
665 for each tuple in the spare buffer. The storage sequence is::
666
667 <spare data page 0><ecc result 0>...<ecc result n>
668
669 ...
670
671 <spare data page n><ecc result 0>...<ecc result n>
672
673 This is a legacy mode used by YAFFS1.
674
675 If the spare area buffer is NULL then only the ECC placement is done
676 according to the given scheme in the nand_oobinfo structure.
677
678 Automatic placement
679 ~~~~~~~~~~~~~~~~~~~
680
681 Automatic placement uses the built in defaults to place the ecc bytes in
682 the spare area. If filesystem data have to be stored / read into the
683 spare area then the calling function must provide a buffer. The buffer
684 size per page is determined by the oobfree array in the nand_oobinfo
685 structure.
686
687 If the spare area buffer is NULL then only the ECC placement is done
688 according to the default builtin scheme.
689
690 Spare area autoplacement default schemes
691 ----------------------------------------
692
693 256 byte pagesize
694 ~~~~~~~~~~~~~~~~~
695
696 ======== ================== ===================================================
697 Offset Content Comment
698 ======== ================== ===================================================
699 0x00 ECC byte 0 Error correction code byte 0
700 0x01 ECC byte 1 Error correction code byte 1
701 0x02 ECC byte 2 Error correction code byte 2
702 0x03 Autoplace 0
703 0x04 Autoplace 1
704 0x05 Bad block marker If any bit in this byte is zero, then this
705 block is bad. This applies only to the first
706 page in a block. In the remaining pages this
707 byte is reserved
708 0x06 Autoplace 2
709 0x07 Autoplace 3
710 ======== ================== ===================================================
711
712 512 byte pagesize
713 ~~~~~~~~~~~~~~~~~
714
715
716 ============= ================== ==============================================
717 Offset Content Comment
718 ============= ================== ==============================================
719 0x00 ECC byte 0 Error correction code byte 0 of the lower
720 256 Byte data in this page
721 0x01 ECC byte 1 Error correction code byte 1 of the lower
722 256 Bytes of data in this page
723 0x02 ECC byte 2 Error correction code byte 2 of the lower
724 256 Bytes of data in this page
725 0x03 ECC byte 3 Error correction code byte 0 of the upper
726 256 Bytes of data in this page
727 0x04 reserved reserved
728 0x05 Bad block marker If any bit in this byte is zero, then this
729 block is bad. This applies only to the first
730 page in a block. In the remaining pages this
731 byte is reserved
732 0x06 ECC byte 4 Error correction code byte 1 of the upper
733 256 Bytes of data in this page
734 0x07 ECC byte 5 Error correction code byte 2 of the upper
735 256 Bytes of data in this page
736 0x08 - 0x0F Autoplace 0 - 7
737 ============= ================== ==============================================
738
739 2048 byte pagesize
740 ~~~~~~~~~~~~~~~~~~
741
742 =========== ================== ================================================
743 Offset Content Comment
744 =========== ================== ================================================
745 0x00 Bad block marker If any bit in this byte is zero, then this block
746 is bad. This applies only to the first page in a
747 block. In the remaining pages this byte is
748 reserved
749 0x01 Reserved Reserved
750 0x02-0x27 Autoplace 0 - 37
751 0x28 ECC byte 0 Error correction code byte 0 of the first
752 256 Byte data in this page
753 0x29 ECC byte 1 Error correction code byte 1 of the first
754 256 Bytes of data in this page
755 0x2A ECC byte 2 Error correction code byte 2 of the first
756 256 Bytes data in this page
757 0x2B ECC byte 3 Error correction code byte 0 of the second
758 256 Bytes of data in this page
759 0x2C ECC byte 4 Error correction code byte 1 of the second
760 256 Bytes of data in this page
761 0x2D ECC byte 5 Error correction code byte 2 of the second
762 256 Bytes of data in this page
763 0x2E ECC byte 6 Error correction code byte 0 of the third
764 256 Bytes of data in this page
765 0x2F ECC byte 7 Error correction code byte 1 of the third
766 256 Bytes of data in this page
767 0x30 ECC byte 8 Error correction code byte 2 of the third
768 256 Bytes of data in this page
769 0x31 ECC byte 9 Error correction code byte 0 of the fourth
770 256 Bytes of data in this page
771 0x32 ECC byte 10 Error correction code byte 1 of the fourth
772 256 Bytes of data in this page
773 0x33 ECC byte 11 Error correction code byte 2 of the fourth
774 256 Bytes of data in this page
775 0x34 ECC byte 12 Error correction code byte 0 of the fifth
776 256 Bytes of data in this page
777 0x35 ECC byte 13 Error correction code byte 1 of the fifth
778 256 Bytes of data in this page
779 0x36 ECC byte 14 Error correction code byte 2 of the fifth
780 256 Bytes of data in this page
781 0x37 ECC byte 15 Error correction code byte 0 of the sixth
782 256 Bytes of data in this page
783 0x38 ECC byte 16 Error correction code byte 1 of the sixth
784 256 Bytes of data in this page
785 0x39 ECC byte 17 Error correction code byte 2 of the sixth
786 256 Bytes of data in this page
787 0x3A ECC byte 18 Error correction code byte 0 of the seventh
788 256 Bytes of data in this page
789 0x3B ECC byte 19 Error correction code byte 1 of the seventh
790 256 Bytes of data in this page
791 0x3C ECC byte 20 Error correction code byte 2 of the seventh
792 256 Bytes of data in this page
793 0x3D ECC byte 21 Error correction code byte 0 of the eighth
794 256 Bytes of data in this page
795 0x3E ECC byte 22 Error correction code byte 1 of the eighth
796 256 Bytes of data in this page
797 0x3F ECC byte 23 Error correction code byte 2 of the eighth
798 256 Bytes of data in this page
799 =========== ================== ================================================
800
801 Filesystem support
802 ==================
803
804 The NAND driver provides all necessary functions for a filesystem via
805 the MTD interface.
806
807 Filesystems must be aware of the NAND peculiarities and restrictions.
808 One major restrictions of NAND Flash is, that you cannot write as often
809 as you want to a page. The consecutive writes to a page, before erasing
810 it again, are restricted to 1-3 writes, depending on the manufacturers
811 specifications. This applies similar to the spare area.
812
813 Therefore NAND aware filesystems must either write in page size chunks
814 or hold a writebuffer to collect smaller writes until they sum up to
815 pagesize. Available NAND aware filesystems: JFFS2, YAFFS.
816
817 The spare area usage to store filesystem data is controlled by the spare
818 area placement functionality which is described in one of the earlier
819 chapters.
820
821 Tools
822 =====
823
824 The MTD project provides a couple of helpful tools to handle NAND Flash.
825
826 - flasherase, flasheraseall: Erase and format FLASH partitions
827
828 - nandwrite: write filesystem images to NAND FLASH
829
830 - nanddump: dump the contents of a NAND FLASH partitions
831
832 These tools are aware of the NAND restrictions. Please use those tools
833 instead of complaining about errors which are caused by non NAND aware
834 access methods.
835
836 Constants
837 =========
838
839 This chapter describes the constants which might be relevant for a
840 driver developer.
841
842 Chip option constants
843 ---------------------
844
845 Constants for chip id table
846 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
847
848 These constants are defined in rawnand.h. They are OR-ed together to
849 describe the chip functionality::
850
851 /* Buswitdh is 16 bit */
852 #define NAND_BUSWIDTH_16 0x00000002
853 /* Device supports partial programming without padding */
854 #define NAND_NO_PADDING 0x00000004
855 /* Chip has cache program function */
856 #define NAND_CACHEPRG 0x00000008
857 /* Chip has copy back function */
858 #define NAND_COPYBACK 0x00000010
859 /* AND Chip which has 4 banks and a confusing page / block
860 * assignment. See Renesas datasheet for further information */
861 #define NAND_IS_AND 0x00000020
862 /* Chip has a array of 4 pages which can be read without
863 * additional ready /busy waits */
864 #define NAND_4PAGE_ARRAY 0x00000040
865
866
867 Constants for runtime options
868 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
869
870 These constants are defined in rawnand.h. They are OR-ed together to
871 describe the functionality::
872
873 /* The hw ecc generator provides a syndrome instead a ecc value on read
874 * This can only work if we have the ecc bytes directly behind the
875 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
876 #define NAND_HWECC_SYNDROME 0x00020000
877
878
879 ECC selection constants
880 -----------------------
881
882 Use these constants to select the ECC algorithm::
883
884 /* No ECC. Usage is not recommended ! */
885 #define NAND_ECC_NONE 0
886 /* Software ECC 3 byte ECC per 256 Byte data */
887 #define NAND_ECC_SOFT 1
888 /* Hardware ECC 3 byte ECC per 256 Byte data */
889 #define NAND_ECC_HW3_256 2
890 /* Hardware ECC 3 byte ECC per 512 Byte data */
891 #define NAND_ECC_HW3_512 3
892 /* Hardware ECC 6 byte ECC per 512 Byte data */
893 #define NAND_ECC_HW6_512 4
894 /* Hardware ECC 8 byte ECC per 512 Byte data */
895 #define NAND_ECC_HW8_512 6
896
897
898 Hardware control related constants
899 ----------------------------------
900
901 These constants describe the requested hardware access function when the
902 boardspecific hardware control function is called::
903
904 /* Select the chip by setting nCE to low */
905 #define NAND_CTL_SETNCE 1
906 /* Deselect the chip by setting nCE to high */
907 #define NAND_CTL_CLRNCE 2
908 /* Select the command latch by setting CLE to high */
909 #define NAND_CTL_SETCLE 3
910 /* Deselect the command latch by setting CLE to low */
911 #define NAND_CTL_CLRCLE 4
912 /* Select the address latch by setting ALE to high */
913 #define NAND_CTL_SETALE 5
914 /* Deselect the address latch by setting ALE to low */
915 #define NAND_CTL_CLRALE 6
916 /* Set write protection by setting WP to high. Not used! */
917 #define NAND_CTL_SETWP 7
918 /* Clear write protection by setting WP to low. Not used! */
919 #define NAND_CTL_CLRWP 8
920
921
922 Bad block table related constants
923 ---------------------------------
924
925 These constants describe the options used for bad block table
926 descriptors::
927
928 /* Options for the bad block table descriptors */
929
930 /* The number of bits used per block in the bbt on the device */
931 #define NAND_BBT_NRBITS_MSK 0x0000000F
932 #define NAND_BBT_1BIT 0x00000001
933 #define NAND_BBT_2BIT 0x00000002
934 #define NAND_BBT_4BIT 0x00000004
935 #define NAND_BBT_8BIT 0x00000008
936 /* The bad block table is in the last good block of the device */
937 #define NAND_BBT_LASTBLOCK 0x00000010
938 /* The bbt is at the given page, else we must scan for the bbt */
939 #define NAND_BBT_ABSPAGE 0x00000020
940 /* bbt is stored per chip on multichip devices */
941 #define NAND_BBT_PERCHIP 0x00000080
942 /* bbt has a version counter at offset veroffs */
943 #define NAND_BBT_VERSION 0x00000100
944 /* Create a bbt if none axists */
945 #define NAND_BBT_CREATE 0x00000200
946 /* Write bbt if necessary */
947 #define NAND_BBT_WRITE 0x00001000
948 /* Read and write back block contents when writing bbt */
949 #define NAND_BBT_SAVECONTENT 0x00002000
950
951
952 Structures
953 ==========
954
955 This chapter contains the autogenerated documentation of the structures
956 which are used in the NAND driver and might be relevant for a driver
957 developer. Each struct member has a short description which is marked
958 with an [XXX] identifier. See the chapter "Documentation hints" for an
959 explanation.
960
961 .. kernel-doc:: include/linux/mtd/rawnand.h
962 :internal:
963
964 Public Functions Provided
965 =========================
966
967 This chapter contains the autogenerated documentation of the NAND kernel
968 API functions which are exported. Each function has a short description
969 which is marked with an [XXX] identifier. See the chapter "Documentation
970 hints" for an explanation.
971
972 .. kernel-doc:: drivers/mtd/nand/raw/nand_base.c
973 :export:
974
975 Internal Functions Provided
976 ===========================
977
978 This chapter contains the autogenerated documentation of the NAND driver
979 internal functions. Each function has a short description which is
980 marked with an [XXX] identifier. See the chapter "Documentation hints"
981 for an explanation. The functions marked with [DEFAULT] might be
982 relevant for a board driver developer.
983
984 .. kernel-doc:: drivers/mtd/nand/raw/nand_base.c
985 :internal:
986
987 .. kernel-doc:: drivers/mtd/nand/raw/nand_bbt.c
988 :internal:
989
990 Credits
991 =======
992
993 The following people have contributed to the NAND driver:
994
995 1. Steven J. Hill\ sjhill@realitydiluted.com
996
997 2. David Woodhouse\ dwmw2@infradead.org
998
999 3. Thomas Gleixner\ tglx@linutronix.de
1000
1001 A lot of users have provided bugfixes, improvements and helping hands
1002 for testing. Thanks a lot.
1003
1004 The following people have contributed to this document:
1005
1006 1. Thomas Gleixner\ tglx@linutronix.de
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