1 ==================================
2 VFIO - "Virtual Function I/O" [1]_
3 ==================================
4
5 Many modern systems now provide DMA and interrupt remapping facilities
6 to help ensure I/O devices behave within the boundaries they've been
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
8 POWER systems with Partitionable Endpoints (PEs) and embedded PowerPC
9 systems such as Freescale PAMU. The VFIO driver is an IOMMU/device
10 agnostic framework for exposing direct device access to userspace, in
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
13
14 Why do we want that? Virtual machines often make use of direct device
15 access ("device assignment") when configured for the highest possible
16 I/O performance. From a device and host perspective, this simply
17 turns the VM into a userspace driver, with the benefits of
18 significantly reduced latency, higher bandwidth, and direct use of
19 bare-metal device drivers [3]_.
20
21 Some applications, particularly in the high performance computing
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
24 and compute accelerators. Prior to VFIO, these drivers had to either
25 go through the full development cycle to become proper upstream
26 driver, be maintained out of tree, or make use of the UIO framework,
27 which has no notion of IOMMU protection, limited interrupt support,
28 and requires root privileges to access things like PCI configuration
29 space.
30
31 The VFIO driver framework intends to unify these, replacing both the
32 KVM PCI specific device assignment code as well as provide a more
33 secure, more featureful userspace driver environment than UIO.
34
35 Groups, Devices, and IOMMUs
36 ---------------------------
37
38 Devices are the main target of any I/O driver. Devices typically
39 create a programming interface made up of I/O access, interrupts,
40 and DMA. Without going into the details of each of these, DMA is
41 by far the most critical aspect for maintaining a secure environment
42 as allowing a device read-write access to system memory imposes the
43 greatest risk to the overall system integrity.
44
45 To help mitigate this risk, many modern IOMMUs now incorporate
46 isolation properties into what was, in many cases, an interface only
47 meant for translation (ie. solving the addressing problems of devices
48 with limited address spaces). With this, devices can now be isolated
49 from each other and from arbitrary memory access, thus allowing
50 things like secure direct assignment of devices into virtual machines.
51
52 This isolation is not always at the granularity of a single device
53 though. Even when an IOMMU is capable of this, properties of devices,
54 interconnects, and IOMMU topologies can each reduce this isolation.
55 For instance, an individual device may be part of a larger multi-
56 function enclosure. While the IOMMU may be able to distinguish
57 between devices within the enclosure, the enclosure may not require
58 transactions between devices to reach the IOMMU. Examples of this
59 could be anything from a multi-function PCI device with backdoors
60 between functions to a non-PCI-ACS (Access Control Services) capable
61 bridge allowing redirection without reaching the IOMMU. Topology
62 can also play a factor in terms of hiding devices. A PCIe-to-PCI
63 bridge masks the devices behind it, making transaction appear as if
64 from the bridge itself. Obviously IOMMU design plays a major factor
65 as well.
66
67 Therefore, while for the most part an IOMMU may have device level
68 granularity, any system is susceptible to reduced granularity. The
69 IOMMU API therefore supports a notion of IOMMU groups. A group is
70 a set of devices which is isolatable from all other devices in the
71 system. Groups are therefore the unit of ownership used by VFIO.
72
73 While the group is the minimum granularity that must be used to
74 ensure secure user access, it's not necessarily the preferred
75 granularity. In IOMMUs which make use of page tables, it may be
76 possible to share a set of page tables between different groups,
77 reducing the overhead both to the platform (reduced TLB thrashing,
78 reduced duplicate page tables), and to the user (programming only
79 a single set of translations). For this reason, VFIO makes use of
80 a container class, which may hold one or more groups. A container
81 is created by simply opening the /dev/vfio/vfio character device.
82
83 On its own, the container provides little functionality, with all
84 but a couple version and extension query interfaces locked away.
85 The user needs to add a group into the container for the next level
86 of functionality. To do this, the user first needs to identify the
87 group associated with the desired device. This can be done using
88 the sysfs links described in the example below. By unbinding the
89 device from the host driver and binding it to a VFIO driver, a new
90 VFIO group will appear for the group as /dev/vfio/$GROUP, where
91 $GROUP is the IOMMU group number of which the device is a member.
92 If the IOMMU group contains multiple devices, each will need to
93 be bound to a VFIO driver before operations on the VFIO group
94 are allowed (it's also sufficient to only unbind the device from
95 host drivers if a VFIO driver is unavailable; this will make the
96 group available, but not that particular device). TBD - interface
97 for disabling driver probing/locking a device.
98
99 Once the group is ready, it may be added to the container by opening
100 the VFIO group character device (/dev/vfio/$GROUP) and using the
101 VFIO_GROUP_SET_CONTAINER ioctl, passing the file descriptor of the
102 previously opened container file. If desired and if the IOMMU driver
103 supports sharing the IOMMU context between groups, multiple groups may
104 be set to the same container. If a group fails to set to a container
105 with existing groups, a new empty container will need to be used
106 instead.
107
108 With a group (or groups) attached to a container, the remaining
109 ioctls become available, enabling access to the VFIO IOMMU interfaces.
110 Additionally, it now becomes possible to get file descriptors for each
111 device within a group using an ioctl on the VFIO group file descriptor.
112
113 The VFIO device API includes ioctls for describing the device, the I/O
114 regions and their read/write/mmap offsets on the device descriptor, as
115 well as mechanisms for describing and registering interrupt
116 notifications.
117
118 VFIO Usage Example
119 ------------------
120
121 Assume user wants to access PCI device 0000:06:0d.0::
122
123 $ readlink /sys/bus/pci/devices/0000:06:0d.0/iommu_group
124 ../../../../kernel/iommu_groups/26
125
126 This device is therefore in IOMMU group 26. This device is on the
127 pci bus, therefore the user will make use of vfio-pci to manage the
128 group::
129
130 # modprobe vfio-pci
131
132 Binding this device to the vfio-pci driver creates the VFIO group
133 character devices for this group::
134
135 $ lspci -n -s 0000:06:0d.0
136 06:0d.0 0401: 1102:0002 (rev 08)
137 # echo 0000:06:0d.0 > /sys/bus/pci/devices/0000:06:0d.0/driver/unbind
138 # echo 1102 0002 > /sys/bus/pci/drivers/vfio-pci/new_id
139
140 Now we need to look at what other devices are in the group to free
141 it for use by VFIO::
142
143 $ ls -l /sys/bus/pci/devices/0000:06:0d.0/iommu_group/devices
144 total 0
145 lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:00:1e.0 ->
146 ../../../../devices/pci0000:00/0000:00:1e.0
147 lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:06:0d.0 ->
148 ../../../../devices/pci0000:00/0000:00:1e.0/0000:06:0d.0
149 lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:06:0d.1 ->
150 ../../../../devices/pci0000:00/0000:00:1e.0/0000:06:0d.1
151
152 This device is behind a PCIe-to-PCI bridge [4]_, therefore we also
153 need to add device 0000:06:0d.1 to the group following the same
154 procedure as above. Device 0000:00:1e.0 is a bridge that does
155 not currently have a host driver, therefore it's not required to
156 bind this device to the vfio-pci driver (vfio-pci does not currently
157 support PCI bridges).
158
159 The final step is to provide the user with access to the group if
160 unprivileged operation is desired (note that /dev/vfio/vfio provides
161 no capabilities on its own and is therefore expected to be set to
162 mode 0666 by the system)::
163
164 # chown user:user /dev/vfio/26
165
166 The user now has full access to all the devices and the iommu for this
167 group and can access them as follows::
168
169 int container, group, device, i;
170 struct vfio_group_status group_status =
171 { .argsz = sizeof(group_status) };
172 struct vfio_iommu_type1_info iommu_info = { .argsz = sizeof(iommu_info) };
173 struct vfio_iommu_type1_dma_map dma_map = { .argsz = sizeof(dma_map) };
174 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
175
176 /* Create a new container */
177 container = open("/dev/vfio/vfio", O_RDWR);
178
179 if (ioctl(container, VFIO_GET_API_VERSION) != VFIO_API_VERSION)
180 /* Unknown API version */
181
182 if (!ioctl(container, VFIO_CHECK_EXTENSION, VFIO_TYPE1_IOMMU))
183 /* Doesn't support the IOMMU driver we want. */
184
185 /* Open the group */
186 group = open("/dev/vfio/26", O_RDWR);
187
188 /* Test the group is viable and available */
189 ioctl(group, VFIO_GROUP_GET_STATUS, &group_status);
190
191 if (!(group_status.flags & VFIO_GROUP_FLAGS_VIABLE))
192 /* Group is not viable (ie, not all devices bound for vfio) */
193
194 /* Add the group to the container */
195 ioctl(group, VFIO_GROUP_SET_CONTAINER, &container);
196
197 /* Enable the IOMMU model we want */
198 ioctl(container, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU);
199
200 /* Get addition IOMMU info */
201 ioctl(container, VFIO_IOMMU_GET_INFO, &iommu_info);
202
203 /* Allocate some space and setup a DMA mapping */
204 dma_map.vaddr = mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
205 MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
206 dma_map.size = 1024 * 1024;
207 dma_map.iova = 0; /* 1MB starting at 0x0 from device view */
208 dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;
209
210 ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map);
211
212 /* Get a file descriptor for the device */
213 device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0");
214
215 /* Test and setup the device */
216 ioctl(device, VFIO_DEVICE_GET_INFO, &device_info);
217
218 for (i = 0; i < device_info.num_regions; i++) {
219 struct vfio_region_info reg = { .argsz = sizeof(reg) };
220
221 reg.index = i;
222
223 ioctl(device, VFIO_DEVICE_GET_REGION_INFO, ®);
224
225 /* Setup mappings... read/write offsets, mmaps
226 * For PCI devices, config space is a region */
227 }
228
229 for (i = 0; i < device_info.num_irqs; i++) {
230 struct vfio_irq_info irq = { .argsz = sizeof(irq) };
231
232 irq.index = i;
233
234 ioctl(device, VFIO_DEVICE_GET_IRQ_INFO, &irq);
235
236 /* Setup IRQs... eventfds, VFIO_DEVICE_SET_IRQS */
237 }
238
239 /* Gratuitous device reset and go... */
240 ioctl(device, VFIO_DEVICE_RESET);
241
242 IOMMUFD and vfio_iommu_type1
243 ----------------------------
244
245 IOMMUFD is the new user API to manage I/O page tables from userspace.
246 It intends to be the portal of delivering advanced userspace DMA
247 features (nested translation [5]_, PASID [6]_, etc.) while also providing
248 a backwards compatibility interface for existing VFIO_TYPE1v2_IOMMU use
249 cases. Eventually the vfio_iommu_type1 driver, as well as the legacy
250 vfio container and group model is intended to be deprecated.
251
252 The IOMMUFD backwards compatibility interface can be enabled two ways.
253 In the first method, the kernel can be configured with
254 CONFIG_IOMMUFD_VFIO_CONTAINER, in which case the IOMMUFD subsystem
255 transparently provides the entire infrastructure for the VFIO
256 container and IOMMU backend interfaces. The compatibility mode can
257 also be accessed if the VFIO container interface, ie. /dev/vfio/vfio is
258 simply symlink'd to /dev/iommu. Note that at the time of writing, the
259 compatibility mode is not entirely feature complete relative to
260 VFIO_TYPE1v2_IOMMU (ex. DMA mapping MMIO) and does not attempt to
261 provide compatibility to the VFIO_SPAPR_TCE_IOMMU interface. Therefore
262 it is not generally advisable at this time to switch from native VFIO
263 implementations to the IOMMUFD compatibility interfaces.
264
265 Long term, VFIO users should migrate to device access through the cdev
266 interface described below, and native access through the IOMMUFD
267 provided interfaces.
268
269 VFIO Device cdev
270 ----------------
271
272 Traditionally user acquires a device fd via VFIO_GROUP_GET_DEVICE_FD
273 in a VFIO group.
274
275 With CONFIG_VFIO_DEVICE_CDEV=y the user can now acquire a device fd
276 by directly opening a character device /dev/vfio/devices/vfioX where
277 "X" is the number allocated uniquely by VFIO for registered devices.
278 cdev interface does not support noiommu devices, so user should use
279 the legacy group interface if noiommu is wanted.
280
281 The cdev only works with IOMMUFD. Both VFIO drivers and applications
282 must adapt to the new cdev security model which requires using
283 VFIO_DEVICE_BIND_IOMMUFD to claim DMA ownership before starting to
284 actually use the device. Once BIND succeeds then a VFIO device can
285 be fully accessed by the user.
286
287 VFIO device cdev doesn't rely on VFIO group/container/iommu drivers.
288 Hence those modules can be fully compiled out in an environment
289 where no legacy VFIO application exists.
290
291 So far SPAPR does not support IOMMUFD yet. So it cannot support device
292 cdev either.
293
294 vfio device cdev access is still bound by IOMMU group semantics, ie. there
295 can be only one DMA owner for the group. Devices belonging to the same
296 group can not be bound to multiple iommufd_ctx or shared between native
297 kernel and vfio bus driver or other driver supporting the driver_managed_dma
298 flag. A violation of this ownership requirement will fail at the
299 VFIO_DEVICE_BIND_IOMMUFD ioctl, which gates full device access.
300
301 Device cdev Example
302 -------------------
303
304 Assume user wants to access PCI device 0000:6a:01.0::
305
306 $ ls /sys/bus/pci/devices/0000:6a:01.0/vfio-dev/
307 vfio0
308
309 This device is therefore represented as vfio0. The user can verify
310 its existence::
311
312 $ ls -l /dev/vfio/devices/vfio0
313 crw------- 1 root root 511, 0 Feb 16 01:22 /dev/vfio/devices/vfio0
314 $ cat /sys/bus/pci/devices/0000:6a:01.0/vfio-dev/vfio0/dev
315 511:0
316 $ ls -l /dev/char/511\:0
317 lrwxrwxrwx 1 root root 21 Feb 16 01:22 /dev/char/511:0 -> ../vfio/devices/vfio0
318
319 Then provide the user with access to the device if unprivileged
320 operation is desired::
321
322 $ chown user:user /dev/vfio/devices/vfio0
323
324 Finally the user could get cdev fd by::
325
326 cdev_fd = open("/dev/vfio/devices/vfio0", O_RDWR);
327
328 An opened cdev_fd doesn't give the user any permission of accessing
329 the device except binding the cdev_fd to an iommufd. After that point
330 then the device is fully accessible including attaching it to an
331 IOMMUFD IOAS/HWPT to enable userspace DMA::
332
333 struct vfio_device_bind_iommufd bind = {
334 .argsz = sizeof(bind),
335 .flags = 0,
336 };
337 struct iommu_ioas_alloc alloc_data = {
338 .size = sizeof(alloc_data),
339 .flags = 0,
340 };
341 struct vfio_device_attach_iommufd_pt attach_data = {
342 .argsz = sizeof(attach_data),
343 .flags = 0,
344 };
345 struct iommu_ioas_map map = {
346 .size = sizeof(map),
347 .flags = IOMMU_IOAS_MAP_READABLE |
348 IOMMU_IOAS_MAP_WRITEABLE |
349 IOMMU_IOAS_MAP_FIXED_IOVA,
350 .__reserved = 0,
351 };
352
353 iommufd = open("/dev/iommu", O_RDWR);
354
355 bind.iommufd = iommufd;
356 ioctl(cdev_fd, VFIO_DEVICE_BIND_IOMMUFD, &bind);
357
358 ioctl(iommufd, IOMMU_IOAS_ALLOC, &alloc_data);
359 attach_data.pt_id = alloc_data.out_ioas_id;
360 ioctl(cdev_fd, VFIO_DEVICE_ATTACH_IOMMUFD_PT, &attach_data);
361
362 /* Allocate some space and setup a DMA mapping */
363 map.user_va = (int64_t)mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
364 MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
365 map.iova = 0; /* 1MB starting at 0x0 from device view */
366 map.length = 1024 * 1024;
367 map.ioas_id = alloc_data.out_ioas_id;
368
369 ioctl(iommufd, IOMMU_IOAS_MAP, &map);
370
371 /* Other device operations as stated in "VFIO Usage Example" */
372
373 VFIO User API
374 -------------------------------------------------------------------------------
375
376 Please see include/uapi/linux/vfio.h for complete API documentation.
377
378 VFIO bus driver API
379 -------------------------------------------------------------------------------
380
381 VFIO bus drivers, such as vfio-pci make use of only a few interfaces
382 into VFIO core. When devices are bound and unbound to the driver,
383 Following interfaces are called when devices are bound to and
384 unbound from the driver::
385
386 int vfio_register_group_dev(struct vfio_device *device);
387 int vfio_register_emulated_iommu_dev(struct vfio_device *device);
388 void vfio_unregister_group_dev(struct vfio_device *device);
389
390 The driver should embed the vfio_device in its own structure and use
391 vfio_alloc_device() to allocate the structure, and can register
392 @init/@release callbacks to manage any private state wrapping the
393 vfio_device::
394
395 vfio_alloc_device(dev_struct, member, dev, ops);
396 void vfio_put_device(struct vfio_device *device);
397
398 vfio_register_group_dev() indicates to the core to begin tracking the
399 iommu_group of the specified dev and register the dev as owned by a VFIO bus
400 driver. Once vfio_register_group_dev() returns it is possible for userspace to
401 start accessing the driver, thus the driver should ensure it is completely
402 ready before calling it. The driver provides an ops structure for callbacks
403 similar to a file operations structure::
404
405 struct vfio_device_ops {
406 char *name;
407 int (*init)(struct vfio_device *vdev);
408 void (*release)(struct vfio_device *vdev);
409 int (*bind_iommufd)(struct vfio_device *vdev,
410 struct iommufd_ctx *ictx, u32 *out_device_id);
411 void (*unbind_iommufd)(struct vfio_device *vdev);
412 int (*attach_ioas)(struct vfio_device *vdev, u32 *pt_id);
413 void (*detach_ioas)(struct vfio_device *vdev);
414 int (*open_device)(struct vfio_device *vdev);
415 void (*close_device)(struct vfio_device *vdev);
416 ssize_t (*read)(struct vfio_device *vdev, char __user *buf,
417 size_t count, loff_t *ppos);
418 ssize_t (*write)(struct vfio_device *vdev, const char __user *buf,
419 size_t count, loff_t *size);
420 long (*ioctl)(struct vfio_device *vdev, unsigned int cmd,
421 unsigned long arg);
422 int (*mmap)(struct vfio_device *vdev, struct vm_area_struct *vma);
423 void (*request)(struct vfio_device *vdev, unsigned int count);
424 int (*match)(struct vfio_device *vdev, char *buf);
425 void (*dma_unmap)(struct vfio_device *vdev, u64 iova, u64 length);
426 int (*device_feature)(struct vfio_device *device, u32 flags,
427 void __user *arg, size_t argsz);
428 };
429
430 Each function is passed the vdev that was originally registered
431 in the vfio_register_group_dev() or vfio_register_emulated_iommu_dev()
432 call above. This allows the bus driver to obtain its private data using
433 container_of().
434
435 ::
436
437 - The init/release callbacks are issued when vfio_device is initialized
438 and released.
439
440 - The open/close device callbacks are issued when the first
441 instance of a file descriptor for the device is created (eg.
442 via VFIO_GROUP_GET_DEVICE_FD) for a user session.
443
444 - The ioctl callback provides a direct pass through for some VFIO_DEVICE_*
445 ioctls.
446
447 - The [un]bind_iommufd callbacks are issued when the device is bound to
448 and unbound from iommufd.
449
450 - The [de]attach_ioas callback is issued when the device is attached to
451 and detached from an IOAS managed by the bound iommufd. However, the
452 attached IOAS can also be automatically detached when the device is
453 unbound from iommufd.
454
455 - The read/write/mmap callbacks implement the device region access defined
456 by the device's own VFIO_DEVICE_GET_REGION_INFO ioctl.
457
458 - The request callback is issued when device is going to be unregistered,
459 such as when trying to unbind the device from the vfio bus driver.
460
461 - The dma_unmap callback is issued when a range of iovas are unmapped
462 in the container or IOAS attached by the device. Drivers which make
463 use of the vfio page pinning interface must implement this callback in
464 order to unpin pages within the dma_unmap range. Drivers must tolerate
465 this callback even before calls to open_device().
466
467 PPC64 sPAPR implementation note
468 -------------------------------
469
470 This implementation has some specifics:
471
472 1) On older systems (POWER7 with P5IOC2/IODA1) only one IOMMU group per
473 container is supported as an IOMMU table is allocated at the boot time,
474 one table per a IOMMU group which is a Partitionable Endpoint (PE)
475 (PE is often a PCI domain but not always).
476
477 Newer systems (POWER8 with IODA2) have improved hardware design which allows
478 to remove this limitation and have multiple IOMMU groups per a VFIO
479 container.
480
481 2) The hardware supports so called DMA windows - the PCI address range
482 within which DMA transfer is allowed, any attempt to access address space
483 out of the window leads to the whole PE isolation.
484
485 3) PPC64 guests are paravirtualized but not fully emulated. There is an API
486 to map/unmap pages for DMA, and it normally maps 1..32 pages per call and
487 currently there is no way to reduce the number of calls. In order to make
488 things faster, the map/unmap handling has been implemented in real mode
489 which provides an excellent performance which has limitations such as
490 inability to do locked pages accounting in real time.
491
492 4) According to sPAPR specification, A Partitionable Endpoint (PE) is an I/O
493 subtree that can be treated as a unit for the purposes of partitioning and
494 error recovery. A PE may be a single or multi-function IOA (IO Adapter), a
495 function of a multi-function IOA, or multiple IOAs (possibly including
496 switch and bridge structures above the multiple IOAs). PPC64 guests detect
497 PCI errors and recover from them via EEH RTAS services, which works on the
498 basis of additional ioctl commands.
499
500 So 4 additional ioctls have been added:
501
502 VFIO_IOMMU_SPAPR_TCE_GET_INFO
503 returns the size and the start of the DMA window on the PCI bus.
504
505 VFIO_IOMMU_ENABLE
506 enables the container. The locked pages accounting
507 is done at this point. This lets user first to know what
508 the DMA window is and adjust rlimit before doing any real job.
509
510 VFIO_IOMMU_DISABLE
511 disables the container.
512
513 VFIO_EEH_PE_OP
514 provides an API for EEH setup, error detection and recovery.
515
516 The code flow from the example above should be slightly changed::
517
518 struct vfio_eeh_pe_op pe_op = { .argsz = sizeof(pe_op), .flags = 0 };
519
520 .....
521 /* Add the group to the container */
522 ioctl(group, VFIO_GROUP_SET_CONTAINER, &container);
523
524 /* Enable the IOMMU model we want */
525 ioctl(container, VFIO_SET_IOMMU, VFIO_SPAPR_TCE_IOMMU)
526
527 /* Get addition sPAPR IOMMU info */
528 vfio_iommu_spapr_tce_info spapr_iommu_info;
529 ioctl(container, VFIO_IOMMU_SPAPR_TCE_GET_INFO, &spapr_iommu_info);
530
531 if (ioctl(container, VFIO_IOMMU_ENABLE))
532 /* Cannot enable container, may be low rlimit */
533
534 /* Allocate some space and setup a DMA mapping */
535 dma_map.vaddr = mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
536 MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
537
538 dma_map.size = 1024 * 1024;
539 dma_map.iova = 0; /* 1MB starting at 0x0 from device view */
540 dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;
541
542 /* Check here is .iova/.size are within DMA window from spapr_iommu_info */
543 ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map);
544
545 /* Get a file descriptor for the device */
546 device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0");
547
548 ....
549
550 /* Gratuitous device reset and go... */
551 ioctl(device, VFIO_DEVICE_RESET);
552
553 /* Make sure EEH is supported */
554 ioctl(container, VFIO_CHECK_EXTENSION, VFIO_EEH);
555
556 /* Enable the EEH functionality on the device */
557 pe_op.op = VFIO_EEH_PE_ENABLE;
558 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
559
560 /* You're suggested to create additional data struct to represent
561 * PE, and put child devices belonging to same IOMMU group to the
562 * PE instance for later reference.
563 */
564
565 /* Check the PE's state and make sure it's in functional state */
566 pe_op.op = VFIO_EEH_PE_GET_STATE;
567 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
568
569 /* Save device state using pci_save_state().
570 * EEH should be enabled on the specified device.
571 */
572
573 ....
574
575 /* Inject EEH error, which is expected to be caused by 32-bits
576 * config load.
577 */
578 pe_op.op = VFIO_EEH_PE_INJECT_ERR;
579 pe_op.err.type = EEH_ERR_TYPE_32;
580 pe_op.err.func = EEH_ERR_FUNC_LD_CFG_ADDR;
581 pe_op.err.addr = 0ul;
582 pe_op.err.mask = 0ul;
583 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
584
585 ....
586
587 /* When 0xFF's returned from reading PCI config space or IO BARs
588 * of the PCI device. Check the PE's state to see if that has been
589 * frozen.
590 */
591 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
592
593 /* Waiting for pending PCI transactions to be completed and don't
594 * produce any more PCI traffic from/to the affected PE until
595 * recovery is finished.
596 */
597
598 /* Enable IO for the affected PE and collect logs. Usually, the
599 * standard part of PCI config space, AER registers are dumped
600 * as logs for further analysis.
601 */
602 pe_op.op = VFIO_EEH_PE_UNFREEZE_IO;
603 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
604
605 /*
606 * Issue PE reset: hot or fundamental reset. Usually, hot reset
607 * is enough. However, the firmware of some PCI adapters would
608 * require fundamental reset.
609 */
610 pe_op.op = VFIO_EEH_PE_RESET_HOT;
611 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
612 pe_op.op = VFIO_EEH_PE_RESET_DEACTIVATE;
613 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
614
615 /* Configure the PCI bridges for the affected PE */
616 pe_op.op = VFIO_EEH_PE_CONFIGURE;
617 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
618
619 /* Restored state we saved at initialization time. pci_restore_state()
620 * is good enough as an example.
621 */
622
623 /* Hopefully, error is recovered successfully. Now, you can resume to
624 * start PCI traffic to/from the affected PE.
625 */
626
627 ....
628
629 5) There is v2 of SPAPR TCE IOMMU. It deprecates VFIO_IOMMU_ENABLE/
630 VFIO_IOMMU_DISABLE and implements 2 new ioctls:
631 VFIO_IOMMU_SPAPR_REGISTER_MEMORY and VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY
632 (which are unsupported in v1 IOMMU).
633
634 PPC64 paravirtualized guests generate a lot of map/unmap requests,
635 and the handling of those includes pinning/unpinning pages and updating
636 mm::locked_vm counter to make sure we do not exceed the rlimit.
637 The v2 IOMMU splits accounting and pinning into separate operations:
638
639 - VFIO_IOMMU_SPAPR_REGISTER_MEMORY/VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY ioctls
640 receive a user space address and size of the block to be pinned.
641 Bisecting is not supported and VFIO_IOMMU_UNREGISTER_MEMORY is expected to
642 be called with the exact address and size used for registering
643 the memory block. The userspace is not expected to call these often.
644 The ranges are stored in a linked list in a VFIO container.
645
646 - VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA ioctls only update the actual
647 IOMMU table and do not do pinning; instead these check that the userspace
648 address is from pre-registered range.
649
650 This separation helps in optimizing DMA for guests.
651
652 6) sPAPR specification allows guests to have an additional DMA window(s) on
653 a PCI bus with a variable page size. Two ioctls have been added to support
654 this: VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE.
655 The platform has to support the functionality or error will be returned to
656 the userspace. The existing hardware supports up to 2 DMA windows, one is
657 2GB long, uses 4K pages and called "default 32bit window"; the other can
658 be as big as entire RAM, use different page size, it is optional - guests
659 create those in run-time if the guest driver supports 64bit DMA.
660
661 VFIO_IOMMU_SPAPR_TCE_CREATE receives a page shift, a DMA window size and
662 a number of TCE table levels (if a TCE table is going to be big enough and
663 the kernel may not be able to allocate enough of physically contiguous
664 memory). It creates a new window in the available slot and returns the bus
665 address where the new window starts. Due to hardware limitation, the user
666 space cannot choose the location of DMA windows.
667
668 VFIO_IOMMU_SPAPR_TCE_REMOVE receives the bus start address of the window
669 and removes it.
670
671 -------------------------------------------------------------------------------
672
673 .. [1] VFIO was originally an acronym for "Virtual Function I/O" in its
674 initial implementation by Tom Lyon while as Cisco. We've since
675 outgrown the acronym, but it's catchy.
676
677 .. [2] "safe" also depends upon a device being "well behaved". It's
678 possible for multi-function devices to have backdoors between
679 functions and even for single function devices to have alternative
680 access to things like PCI config space through MMIO registers. To
681 guard against the former we can include additional precautions in the
682 IOMMU driver to group multi-function PCI devices together
683 (iommu=group_mf). The latter we can't prevent, but the IOMMU should
684 still provide isolation. For PCI, SR-IOV Virtual Functions are the
685 best indicator of "well behaved", as these are designed for
686 virtualization usage models.
687
688 .. [3] As always there are trade-offs to virtual machine device
689 assignment that are beyond the scope of VFIO. It's expected that
690 future IOMMU technologies will reduce some, but maybe not all, of
691 these trade-offs.
692
693 .. [4] In this case the device is below a PCI bridge, so transactions
694 from either function of the device are indistinguishable to the iommu::
695
696 -[0000:00]-+-1e.0-[06]--+-0d.0
697 \-0d.1
698
699 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90)
700
701 .. [5] Nested translation is an IOMMU feature which supports two stage
702 address translations. This improves the address translation efficiency
703 in IOMMU virtualization.
704
705 .. [6] PASID stands for Process Address Space ID, introduced by PCI
706 Express. It is a prerequisite for Shared Virtual Addressing (SVA)
707 and Scalable I/O Virtualization (Scalable IOV).
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