1 =========================== 2 drm/i915 Intel GFX Driver 3 =========================== 4 5 The drm/i915 driver supports all (with the exception of some very early 6 models) integrated GFX chipsets with both Intel display and rendering 7 blocks. This excludes a set of SoC platforms with an SGX rendering unit, 8 those have basic support through the gma500 drm driver. 9 10 Core Driver Infrastructure 11 ========================== 12 13 This section covers core driver infrastructure used by both the display 14 and the GEM parts of the driver. 15 16 Runtime Power Management 17 ------------------------ 18 19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 20 :doc: runtime pm 21 22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 23 :internal: 24 25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c 26 :internal: 27 28 Interrupt Handling 29 ------------------ 30 31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 32 :doc: interrupt handling 33 34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init 36 37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 38 :functions: intel_runtime_pm_disable_interrupts 39 40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 41 :functions: intel_runtime_pm_enable_interrupts 42 43 Intel GVT-g Guest Support(vGPU) 44 ------------------------------- 45 46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 47 :doc: Intel GVT-g guest support 48 49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 50 :internal: 51 52 Intel GVT-g Host Support(vGPU device model) 53 ------------------------------------------- 54 55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 56 :doc: Intel GVT-g host support 57 58 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 59 :internal: 60 61 Workarounds 62 ----------- 63 64 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c 65 :doc: Hardware workarounds 66 67 Display Hardware Handling 68 ========================= 69 70 This section covers everything related to the display hardware including 71 the mode setting infrastructure, plane, sprite and cursor handling and 72 display, output probing and related topics. 73 74 Mode Setting Infrastructure 75 --------------------------- 76 77 The i915 driver is thus far the only DRM driver which doesn't use the 78 common DRM helper code to implement mode setting sequences. Thus it has 79 its own tailor-made infrastructure for executing a display configuration 80 change. 81 82 Frontbuffer Tracking 83 -------------------- 84 85 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 86 :doc: frontbuffer tracking 87 88 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h 89 :internal: 90 91 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 92 :internal: 93 94 Display FIFO Underrun Reporting 95 ------------------------------- 96 97 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 98 :doc: fifo underrun handling 99 100 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 101 :internal: 102 103 Plane Configuration 104 ------------------- 105 106 This section covers plane configuration and composition with the primary 107 plane, sprites, cursors and overlays. This includes the infrastructure 108 to do atomic vsync'ed updates of all this state and also tightly coupled 109 topics like watermark setup and computation, framebuffer compression and 110 panel self refresh. 111 112 Atomic Plane Helpers 113 -------------------- 114 115 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 116 :doc: atomic plane helpers 117 118 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 119 :internal: 120 121 Asynchronous Page Flip 122 ---------------------- 123 124 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c 125 :doc: asynchronous flip implementation 126 127 Output Probing 128 -------------- 129 130 This section covers output probing and related infrastructure like the 131 hotplug interrupt storm detection and mitigation code. Note that the 132 i915 driver still uses most of the common DRM helper code for output 133 probing, so those sections fully apply. 134 135 Hotplug 136 ------- 137 138 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 139 :doc: Hotplug 140 141 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 142 :internal: 143 144 High Definition Audio 145 --------------------- 146 147 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 148 :doc: High Definition Audio over HDMI and Display Port 149 150 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 151 :internal: 152 153 .. kernel-doc:: include/drm/intel/i915_component.h 154 :internal: 155 156 Intel HDMI LPE Audio Support 157 ---------------------------- 158 159 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 160 :doc: LPE Audio integration for HDMI or DP playback 161 162 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 163 :internal: 164 165 Panel Self Refresh PSR (PSR/SRD) 166 -------------------------------- 167 168 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 169 :doc: Panel Self Refresh (PSR/SRD) 170 171 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 172 :internal: 173 174 Frame Buffer Compression (FBC) 175 ------------------------------ 176 177 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 178 :doc: Frame Buffer Compression (FBC) 179 180 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 181 :internal: 182 183 Display Refresh Rate Switching (DRRS) 184 ------------------------------------- 185 186 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 187 :doc: Display Refresh Rate Switching (DRRS) 188 189 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 190 :internal: 191 192 DPIO 193 ---- 194 195 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c 196 :doc: DPIO 197 198 DMC Firmware Support 199 -------------------- 200 201 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 202 :doc: DMC Firmware Support 203 204 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 205 :internal: 206 207 DMC wakelock support 208 -------------------- 209 210 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c 211 :doc: DMC wakelock support 212 213 Video BIOS Table (VBT) 214 ---------------------- 215 216 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 217 :doc: Video BIOS Table (VBT) 218 219 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 220 :internal: 221 222 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h 223 :internal: 224 225 Display clocks 226 -------------- 227 228 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 229 :doc: CDCLK / RAWCLK 230 231 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 232 :internal: 233 234 Display PLLs 235 ------------ 236 237 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 238 :doc: Display PLLs 239 240 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 241 :internal: 242 243 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h 244 :internal: 245 246 Display State Buffer 247 -------------------- 248 249 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 250 :doc: DSB 251 252 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 253 :internal: 254 255 GT Programming 256 ============== 257 258 Multicast/Replicated (MCR) Registers 259 ------------------------------------ 260 261 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c 262 :doc: GT Multicast/Replicated (MCR) Register Support 263 264 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c 265 :internal: 266 267 Memory Management and Command Submission 268 ======================================== 269 270 This sections covers all things related to the GEM implementation in the 271 i915 driver. 272 273 Intel GPU Basics 274 ---------------- 275 276 An Intel GPU has multiple engines. There are several engine types: 277 278 - Render Command Streamer (RCS). An engine for rendering 3D and 279 performing compute. 280 - Blitting Command Streamer (BCS). An engine for performing blitting and/or 281 copying operations. 282 - Video Command Streamer. An engine used for video encoding and decoding. Also 283 sometimes called 'BSD' in hardware documentation. 284 - Video Enhancement Command Streamer (VECS). An engine for video enhancement. 285 Also sometimes called 'VEBOX' in hardware documentation. 286 - Compute Command Streamer (CCS). An engine that has access to the media and 287 GPGPU pipelines, but not the 3D pipeline. 288 - Graphics Security Controller (GSCCS). A dedicated engine for internal 289 communication with GSC controller on security related tasks like 290 High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), 291 and HuC firmware authentication. 292 293 The Intel GPU family is a family of integrated GPU's using Unified 294 Memory Access. For having the GPU "do work", user space will feed the 295 GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` 296 or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will 297 instruct the GPU to perform work (for example rendering) and that work 298 needs memory from which to read and memory to which to write. All memory 299 is encapsulated within GEM buffer objects (usually created with the ioctl 300 `DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU 301 to create will also list all GEM buffer objects that the batchbuffer reads 302 and/or writes. For implementation details of memory management see 303 `GEM BO Management Implementation Details`_. 304 305 The i915 driver allows user space to create a context via the ioctl 306 `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit 307 integer. Such a context should be viewed by user-space as -loosely- 308 analogous to the idea of a CPU process of an operating system. The i915 309 driver guarantees that commands issued to a fixed context are to be 310 executed so that writes of a previously issued command are seen by 311 reads of following commands. Actions issued between different contexts 312 (even if from the same file descriptor) are NOT given that guarantee 313 and the only way to synchronize across contexts (even from the same 314 file descriptor) is through the use of fences. At least as far back as 315 Gen4, also have that a context carries with it a GPU HW context; 316 the HW context is essentially (most of at least) the state of a GPU. 317 In addition to the ordering guarantees, the kernel will restore GPU 318 state via HW context when commands are issued to a context, this saves 319 user space the need to restore (most of at least) the GPU state at the 320 start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer 321 work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) 322 to identify what context to use with the command. 323 324 The GPU has its own memory management and address space. The kernel 325 driver maintains the memory translation table for the GPU. For older 326 GPUs (i.e. those before Gen8), there is a single global such translation 327 table, a global Graphics Translation Table (GTT). For newer generation 328 GPUs each context has its own translation table, called Per-Process 329 Graphics Translation Table (PPGTT). Of important note, is that although 330 PPGTT is named per-process it is actually per context. When user space 331 submits a batchbuffer, the kernel walks the list of GEM buffer objects 332 used by the batchbuffer and guarantees that not only is the memory of 333 each such GEM buffer object resident but it is also present in the 334 (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, 335 then it is given an address. Two consequences of this are: the kernel 336 needs to edit the batchbuffer submitted to write the correct value of 337 the GPU address when a GEM BO is assigned a GPU address and the kernel 338 might evict a different GEM BO from the (PP)GTT to make address room 339 for another GEM BO. Consequently, the ioctls submitting a batchbuffer 340 for execution also include a list of all locations within buffers that 341 refer to GPU-addresses so that the kernel can edit the buffer correctly. 342 This process is dubbed relocation. 343 344 Locking Guidelines 345 ------------------ 346 347 .. note:: 348 This is a description of how the locking should be after 349 refactoring is done. Does not necessarily reflect what the locking 350 looks like while WIP. 351 352 #. All locking rules and interface contracts with cross-driver interfaces 353 (dma-buf, dma_fence) need to be followed. 354 355 #. No struct_mutex anywhere in the code 356 357 #. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx 358 is to be hoisted at highest level and passed down within i915_gem_ctx 359 in the call chain 360 361 #. While holding lru/memory manager (buddy, drm_mm, whatever) locks 362 system memory allocations are not allowed 363 364 * Enforce this by priming lockdep (with fs_reclaim). If we 365 allocate memory while holding these looks we get a rehash 366 of the shrinker vs. struct_mutex saga, and that would be 367 real bad. 368 369 #. Do not nest different lru/memory manager locks within each other. 370 Take them in turn to update memory allocations, relying on the object’s 371 dma_resv ww_mutex to serialize against other operations. 372 373 #. The suggestion for lru/memory managers locks is that they are small 374 enough to be spinlocks. 375 376 #. All features need to come with exhaustive kernel selftests and/or 377 IGT tests when appropriate 378 379 #. All LMEM uAPI paths need to be fully restartable (_interruptible() 380 for all locks/waits/sleeps) 381 382 * Error handling validation through signal injection. 383 Still the best strategy we have for validating GEM uAPI 384 corner cases. 385 Must be excessively used in the IGT, and we need to check 386 that we really have full path coverage of all error cases. 387 388 * -EDEADLK handling with ww_mutex 389 390 GEM BO Management Implementation Details 391 ---------------------------------------- 392 393 .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 394 :doc: Virtual Memory Address 395 396 Buffer Object Eviction 397 ---------------------- 398 399 This section documents the interface functions for evicting buffer 400 objects to make space available in the virtual gpu address spaces. Note 401 that this is mostly orthogonal to shrinking buffer objects caches, which 402 has the goal to make main memory (shared with the gpu through the 403 unified memory architecture) available. 404 405 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c 406 :internal: 407 408 Buffer Object Memory Shrinking 409 ------------------------------ 410 411 This section documents the interface function for shrinking memory usage 412 of buffer object caches. Shrinking is used to make main memory 413 available. Note that this is mostly orthogonal to evicting buffer 414 objects, which has the goal to make space in gpu virtual address spaces. 415 416 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 417 :internal: 418 419 Batchbuffer Parsing 420 ------------------- 421 422 .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 423 :doc: batch buffer command parser 424 425 .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 426 :internal: 427 428 User Batchbuffer Execution 429 -------------------------- 430 431 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h 432 433 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 434 :doc: User command execution 435 436 Scheduling 437 ---------- 438 .. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h 439 :functions: i915_sched_engine 440 441 Logical Rings, Logical Ring Contexts and Execlists 442 -------------------------------------------------- 443 444 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_execlists_submission.c 445 :doc: Logical Rings, Logical Ring Contexts and Execlists 446 447 Global GTT views 448 ---------------- 449 450 .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 451 :doc: Global GTT views 452 453 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c 454 :internal: 455 456 GTT Fences and Swizzling 457 ------------------------ 458 459 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 460 :internal: 461 462 Global GTT Fence Handling 463 ~~~~~~~~~~~~~~~~~~~~~~~~~ 464 465 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 466 :doc: fence register handling 467 468 Hardware Tiling and Swizzling Details 469 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 470 471 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 472 :doc: tiling swizzling details 473 474 Object Tiling IOCTLs 475 -------------------- 476 477 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 478 :internal: 479 480 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 481 :doc: buffer object tiling 482 483 Protected Objects 484 ----------------- 485 486 .. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c 487 :doc: PXP 488 489 .. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h 490 491 Microcontrollers 492 ================ 493 494 Starting from gen9, three microcontrollers are available on the HW: the 495 graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the 496 display microcontroller (DMC). The driver is responsible for loading the 497 firmwares on the microcontrollers; the GuC and HuC firmwares are transferred 498 to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. 499 500 WOPCM 501 ----- 502 503 WOPCM Layout 504 ~~~~~~~~~~~~ 505 506 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_wopcm.c 507 :doc: WOPCM Layout 508 509 GuC 510 --- 511 512 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 513 :doc: GuC 514 515 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h 516 517 GuC Firmware Layout 518 ~~~~~~~~~~~~~~~~~~~ 519 520 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 521 :doc: Firmware Layout 522 523 GuC Memory Management 524 ~~~~~~~~~~~~~~~~~~~~~ 525 526 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 527 :doc: GuC Memory Management 528 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 529 :functions: intel_guc_allocate_vma 530 531 532 GuC-specific firmware loader 533 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 534 535 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 536 :internal: 537 538 GuC-based command submission 539 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 540 541 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 542 :doc: GuC-based command submission 543 544 GuC ABI 545 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 546 547 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h 548 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h 549 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 550 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 551 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 552 553 HuC 554 --- 555 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 556 :doc: HuC 557 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 558 :functions: intel_huc_auth 559 560 HuC Memory Management 561 ~~~~~~~~~~~~~~~~~~~~~ 562 563 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 564 :doc: HuC Memory Management 565 566 HuC Firmware Layout 567 ~~~~~~~~~~~~~~~~~~~ 568 The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ 569 570 DMC 571 --- 572 See `DMC Firmware Support`_ 573 574 Tracing 575 ======= 576 577 This sections covers all things related to the tracepoints implemented 578 in the i915 driver. 579 580 i915_ppgtt_create and i915_ppgtt_release 581 ---------------------------------------- 582 583 .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 584 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints 585 586 i915_context_create and i915_context_free 587 ----------------------------------------- 588 589 .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 590 :doc: i915_context_create and i915_context_free tracepoints 591 592 Perf 593 ==== 594 595 Overview 596 -------- 597 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 598 :doc: i915 Perf Overview 599 600 Comparison with Core Perf 601 ------------------------- 602 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 603 :doc: i915 Perf History and Comparison with Core Perf 604 605 i915 Driver Entry Points 606 ------------------------ 607 608 This section covers the entrypoints exported outside of i915_perf.c to 609 integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl. 610 611 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 612 :functions: i915_perf_init 613 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 614 :functions: i915_perf_fini 615 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 616 :functions: i915_perf_register 617 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 618 :functions: i915_perf_unregister 619 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 620 :functions: i915_perf_open_ioctl 621 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 622 :functions: i915_perf_release 623 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 624 :functions: i915_perf_add_config_ioctl 625 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 626 :functions: i915_perf_remove_config_ioctl 627 628 i915 Perf Stream 629 ---------------- 630 631 This section covers the stream-semantics-agnostic structures and functions 632 for representing an i915 perf stream FD and associated file operations. 633 634 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 635 :functions: i915_perf_stream 636 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 637 :functions: i915_perf_stream_ops 638 639 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 640 :functions: read_properties_unlocked 641 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 642 :functions: i915_perf_open_ioctl_locked 643 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 644 :functions: i915_perf_destroy_locked 645 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 646 :functions: i915_perf_read 647 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 648 :functions: i915_perf_ioctl 649 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 650 :functions: i915_perf_enable_locked 651 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 652 :functions: i915_perf_disable_locked 653 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 654 :functions: i915_perf_poll 655 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 656 :functions: i915_perf_poll_locked 657 658 i915 Perf Observation Architecture Stream 659 ----------------------------------------- 660 661 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 662 :functions: i915_oa_ops 663 664 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 665 :functions: i915_oa_stream_init 666 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 667 :functions: i915_oa_read 668 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 669 :functions: i915_oa_stream_enable 670 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 671 :functions: i915_oa_stream_disable 672 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 673 :functions: i915_oa_wait_unlocked 674 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 675 :functions: i915_oa_poll_wait 676 677 Other i915 Perf Internals 678 ------------------------- 679 680 This section simply includes all other currently documented i915 perf internals, 681 in no particular order, but may include some more minor utilities or platform 682 specific details than found in the more high-level sections. 683 684 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 685 :internal: 686 :no-identifiers: 687 i915_perf_init 688 i915_perf_fini 689 i915_perf_register 690 i915_perf_unregister 691 i915_perf_open_ioctl 692 i915_perf_release 693 i915_perf_add_config_ioctl 694 i915_perf_remove_config_ioctl 695 read_properties_unlocked 696 i915_perf_open_ioctl_locked 697 i915_perf_destroy_locked 698 i915_perf_read i915_perf_ioctl 699 i915_perf_enable_locked 700 i915_perf_disable_locked 701 i915_perf_poll i915_perf_poll_locked 702 i915_oa_stream_init i915_oa_read 703 i915_oa_stream_enable 704 i915_oa_stream_disable 705 i915_oa_wait_unlocked 706 i915_oa_poll_wait 707 708 Style 709 ===== 710 711 The drm/i915 driver codebase has some style rules in addition to (and, in some 712 cases, deviating from) the kernel coding style. 713 714 Register macro definition style 715 ------------------------------- 716 717 The style guide for ``i915_reg.h``. 718 719 .. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h 720 :doc: The i915 register macro definition style guide 721 722 .. _i915-usage-stats: 723 724 i915 DRM client usage stats implementation 725 ========================================== 726 727 The drm/i915 driver implements the DRM client usage stats specification as 728 documented in :ref:`drm-client-usage-stats`. 729 730 Example of the output showing the implemented key value pairs and entirety of 731 the currently possible format options: 732 733 :: 734 735 pos: 0 736 flags: 0100002 737 mnt_id: 21 738 drm-driver: i915 739 drm-pdev: 0000:00:02.0 740 drm-client-id: 7 741 drm-engine-render: 9288864723 ns 742 drm-engine-copy: 2035071108 ns 743 drm-engine-video: 0 ns 744 drm-engine-capacity-video: 2 745 drm-engine-video-enhance: 0 ns 746 747 Possible `drm-engine-` key names are: `render`, `copy`, `video` and 748 `video-enhance`.
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