1 .. SPDX-License-Identifier: GPL-2.0-or-later
2
3 =====================
4 Kernel driver w1-uart
5 =====================
6
7 Author: Christoph Winklhofer <cj.winklhofer@gmail.com>
8
9
10 Description
11 -----------
12
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
16
17 .. _"Using a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-uart-to-implement-a-1wire-bus-master.html
18
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
22 1-Wire read bit, write bit or reset pulse.
23
24 For instance the timing pattern for a 1-Wire reset and presence detect uses
25 the baud-rate 9600, i.e. 104.2 us per bit. The transmitted byte 0xf0 over
26 UART (least significant bit first, start-bit low) sets the reset low time
27 for 1-Wire to 521 us. A present 1-Wire device changes the received byte by
28 pulling the line low, which is used by the driver to evaluate the result of
29 the 1-Wire operation.
30
31 Similar for a 1-Wire read bit or write bit, which uses the baud-rate
32 115200, i.e. 8.7 us per bit. The transmitted byte 0x80 is used for a
33 Write-0 operation (low time 69.6us) and the byte 0xff for Read-0, Read-1
34 and Write-1 (low time 8.7us).
35
36 The default baud-rate for reset and presence detection is 9600 and for
37 a 1-Wire read or write operation 115200. In case the actual baud-rate
38 is different from the requested one, the transmitted byte is adapted
39 to generate the 1-Wire timing patterns.
40
41
42 Usage
43 -----
44
45 Specify the UART 1-wire bus in the device tree by adding the single child
46 onewire to the serial node (e.g. uart0). For example:
47 ::
48
49 @uart0 {
50 ...
51 onewire {
52 compatible = "w1-uart";
53 };
54 };
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