1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ALPHA_PGTABLE_H
3 #define _ALPHA_PGTABLE_H
4
5 #include <asm-generic/pgtable-nopud.h>
6
7 /*
8 * This file contains the functions and defines necessary to modify and use
9 * the Alpha page table tree.
10 *
11 * This hopefully works with any standard Alpha page-size, as defined
12 * in <asm/page.h> (currently 8192).
13 */
14 #include <linux/mmzone.h>
15
16 #include <asm/page.h>
17 #include <asm/processor.h> /* For TASK_SIZE */
18 #include <asm/machvec.h>
19 #include <asm/setup.h>
20
21 struct mm_struct;
22 struct vm_area_struct;
23
24 /* Certain architectures need to do special things when PTEs
25 * within a page table are directly modified. Thus, the following
26 * hook is made available.
27 */
28 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
29
30 /* PMD_SHIFT determines the size of the area a second-level page table can map */
31 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
32 #define PMD_SIZE (1UL << PMD_SHIFT)
33 #define PMD_MASK (~(PMD_SIZE-1))
34
35 /* PGDIR_SHIFT determines what a third-level page table entry can map */
36 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
37 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
38 #define PGDIR_MASK (~(PGDIR_SIZE-1))
39
40 /*
41 * Entries per page directory level: the Alpha is three-level, with
42 * all levels having a one-page page table.
43 */
44 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
45 #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
46 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
47 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
48
49 /* Number of pointers that fit on a page: this will go away. */
50 #define PTRS_PER_PAGE (1UL << (PAGE_SHIFT-3))
51
52 #ifdef CONFIG_ALPHA_LARGE_VMALLOC
53 #define VMALLOC_START 0xfffffe0000000000
54 #else
55 #define VMALLOC_START (-2*PGDIR_SIZE)
56 #endif
57 #define VMALLOC_END (-PGDIR_SIZE)
58
59 /*
60 * OSF/1 PAL-code-imposed page table bits
61 */
62 #define _PAGE_VALID 0x0001
63 #define _PAGE_FOR 0x0002 /* used for page protection (fault on read) */
64 #define _PAGE_FOW 0x0004 /* used for page protection (fault on write) */
65 #define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */
66 #define _PAGE_ASM 0x0010
67 #define _PAGE_KRE 0x0100 /* xxx - see below on the "accessed" bit */
68 #define _PAGE_URE 0x0200 /* xxx */
69 #define _PAGE_KWE 0x1000 /* used to do the dirty bit in software */
70 #define _PAGE_UWE 0x2000 /* used to do the dirty bit in software */
71
72 /* .. and these are ours ... */
73 #define _PAGE_DIRTY 0x20000
74 #define _PAGE_ACCESSED 0x40000
75
76 /* We borrow bit 39 to store the exclusive marker in swap PTEs. */
77 #define _PAGE_SWP_EXCLUSIVE 0x8000000000UL
78
79 /*
80 * NOTE! The "accessed" bit isn't necessarily exact: it can be kept exactly
81 * by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it.
82 * Under Linux/AXP, the "accessed" bit just means "read", and I'll just use
83 * the KRE/URE bits to watch for it. That way we don't need to overload the
84 * KWE/UWE bits with both handling dirty and accessed.
85 *
86 * Note that the kernel uses the accessed bit just to check whether to page
87 * out a page or not, so it doesn't have to be exact anyway.
88 */
89
90 #define __DIRTY_BITS (_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE)
91 #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE)
92
93 #define _PFN_MASK 0xFFFFFFFF00000000UL
94
95 #define _PAGE_TABLE (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS)
96 #define _PAGE_CHG_MASK (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS)
97
98 /*
99 * All the normal masks have the "page accessed" bits on, as any time they are used,
100 * the page is accessed. They are cleared only by the page-out routines
101 */
102 #define PAGE_NONE __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE)
103 #define PAGE_SHARED __pgprot(_PAGE_VALID | __ACCESS_BITS)
104 #define PAGE_COPY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
105 #define PAGE_READONLY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
106 #define PAGE_KERNEL __pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE)
107
108 #define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x))
109
110 #define _PAGE_P(x) _PAGE_NORMAL((x) | (((x) & _PAGE_FOW)?0:_PAGE_FOW))
111 #define _PAGE_S(x) _PAGE_NORMAL(x)
112
113 /*
114 * The hardware can handle write-only mappings, but as the Alpha
115 * architecture does byte-wide writes with a read-modify-write
116 * sequence, it's not practical to have write-without-read privs.
117 * Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in
118 * arch/alpha/mm/fault.c)
119 */
120 /* xwr */
121
122 /*
123 * pgprot_noncached() is only for infiniband pci support, and a real
124 * implementation for RAM would be more complicated.
125 */
126 #define pgprot_noncached(prot) (prot)
127
128 /*
129 * BAD_PAGETABLE is used when we need a bogus page-table, while
130 * BAD_PAGE is used for a bogus page.
131 *
132 * ZERO_PAGE is a global shared page that is always zero: used
133 * for zero-mapped memory areas etc..
134 */
135 extern pte_t __bad_page(void);
136 extern pmd_t * __bad_pagetable(void);
137
138 extern unsigned long __zero_page(void);
139
140 #define BAD_PAGETABLE __bad_pagetable()
141 #define BAD_PAGE __bad_page()
142 #define ZERO_PAGE(vaddr) (virt_to_page(ZERO_PGE))
143
144 /* number of bits that fit into a memory pointer */
145 #define BITS_PER_PTR (8*sizeof(unsigned long))
146
147 /* to align the pointer to a pointer address */
148 #define PTR_MASK (~(sizeof(void*)-1))
149
150 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
151 #define SIZEOF_PTR_LOG2 3
152
153 /* to find an entry in a page-table */
154 #define PAGE_PTR(address) \
155 ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
156
157 /*
158 * On certain platforms whose physical address space can overlap KSEG,
159 * namely EV6 and above, we must re-twiddle the physaddr to restore the
160 * correct high-order bits.
161 *
162 * This is extremely confusing until you realize that this is actually
163 * just working around a userspace bug. The X server was intending to
164 * provide the physical address but instead provided the KSEG address.
165 * Or tried to, except it's not representable.
166 *
167 * On Tsunami there's nothing meaningful at 0x40000000000, so this is
168 * a safe thing to do. Come the first core logic that does put something
169 * in this area -- memory or whathaveyou -- then this hack will have
170 * to go away. So be prepared!
171 */
172
173 #if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG)
174 #error "EV6-only feature in a generic kernel"
175 #endif
176 #if defined(CONFIG_ALPHA_GENERIC) || \
177 (defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG))
178 #define KSEG_PFN (0xc0000000000UL >> PAGE_SHIFT)
179 #define PHYS_TWIDDLE(pfn) \
180 ((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \
181 ? ((pfn) ^= KSEG_PFN) : (pfn))
182 #else
183 #define PHYS_TWIDDLE(pfn) (pfn)
184 #endif
185
186 /*
187 * Conversion functions: convert a page and protection to a page entry,
188 * and a page entry and page directory to the page they refer to.
189 */
190 #define page_to_pa(page) (page_to_pfn(page) << PAGE_SHIFT)
191 #define PFN_PTE_SHIFT 32
192 #define pte_pfn(pte) (pte_val(pte) >> PFN_PTE_SHIFT)
193
194 #define pte_page(pte) pfn_to_page(pte_pfn(pte))
195 #define mk_pte(page, pgprot) \
196 ({ \
197 pte_t pte; \
198 \
199 pte_val(pte) = (page_to_pfn(page) << 32) | pgprot_val(pgprot); \
200 pte; \
201 })
202
203 extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot)
204 { pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; }
205
206 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
207 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
208
209 extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
210 { pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
211
212 extern inline void pud_set(pud_t * pudp, pmd_t * pmdp)
213 { pud_val(*pudp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
214
215
216 extern inline unsigned long
217 pmd_page_vaddr(pmd_t pmd)
218 {
219 return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET;
220 }
221
222 #define pmd_pfn(pmd) (pmd_val(pmd) >> 32)
223 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> 32))
224 #define pud_page(pud) (pfn_to_page(pud_val(pud) >> 32))
225
226 extern inline pmd_t *pud_pgtable(pud_t pgd)
227 {
228 return (pmd_t *)(PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)));
229 }
230
231 extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
232 extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_VALID; }
233 extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
234 {
235 pte_val(*ptep) = 0;
236 }
237
238 extern inline int pmd_none(pmd_t pmd) { return !pmd_val(pmd); }
239 extern inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; }
240 extern inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _PAGE_VALID; }
241 extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = 0; }
242
243 extern inline int pud_none(pud_t pud) { return !pud_val(pud); }
244 extern inline int pud_bad(pud_t pud) { return (pud_val(pud) & ~_PFN_MASK) != _PAGE_TABLE; }
245 extern inline int pud_present(pud_t pud) { return pud_val(pud) & _PAGE_VALID; }
246 extern inline void pud_clear(pud_t * pudp) { pud_val(*pudp) = 0; }
247
248 /*
249 * The following only work if pte_present() is true.
250 * Undefined behaviour if not..
251 */
252 extern inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_FOW); }
253 extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
254 extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
255
256 extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOW; return pte; }
257 extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(__DIRTY_BITS); return pte; }
258 extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~(__ACCESS_BITS); return pte; }
259 extern inline pte_t pte_mkwrite_novma(pte_t pte){ pte_val(pte) &= ~_PAGE_FOW; return pte; }
260 extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= __DIRTY_BITS; return pte; }
261 extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; return pte; }
262
263 /*
264 * The smp_rmb() in the following functions are required to order the load of
265 * *dir (the pointer in the top level page table) with any subsequent load of
266 * the returned pmd_t *ret (ret is data dependent on *dir).
267 *
268 * If this ordering is not enforced, the CPU might load an older value of
269 * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
270 * more details.
271 *
272 * Note that we never change the mm->pgd pointer after the task is running, so
273 * pgd_offset does not require such a barrier.
274 */
275
276 /* Find an entry in the second-level page table.. */
277 extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address)
278 {
279 pmd_t *ret = pud_pgtable(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
280 smp_rmb(); /* see above */
281 return ret;
282 }
283 #define pmd_offset pmd_offset
284
285 /* Find an entry in the third-level page table.. */
286 extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
287 {
288 pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
289 + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
290 smp_rmb(); /* see above */
291 return ret;
292 }
293 #define pte_offset_kernel pte_offset_kernel
294
295 extern pgd_t swapper_pg_dir[1024];
296
297 /*
298 * The Alpha doesn't have any external MMU info: the kernel page
299 * tables contain all the necessary information.
300 */
301 extern inline void update_mmu_cache(struct vm_area_struct * vma,
302 unsigned long address, pte_t *ptep)
303 {
304 }
305
306 static inline void update_mmu_cache_range(struct vm_fault *vmf,
307 struct vm_area_struct *vma, unsigned long address,
308 pte_t *ptep, unsigned int nr)
309 {
310 }
311
312 /*
313 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
314 * are !pte_none() && !pte_present().
315 *
316 * Format of swap PTEs:
317 *
318 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
319 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
320 * <------------------- offset ------------------> E <--- type -->
321 *
322 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
323 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
324 * <--------------------------- zeroes -------------------------->
325 *
326 * E is the exclusive marker that is not stored in swap entries.
327 */
328 extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
329 { pte_t pte; pte_val(pte) = ((type & 0x7f) << 32) | (offset << 40); return pte; }
330
331 #define __swp_type(x) (((x).val >> 32) & 0x7f)
332 #define __swp_offset(x) ((x).val >> 40)
333 #define __swp_entry(type, off) ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) })
334 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
335 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
336
337 static inline int pte_swp_exclusive(pte_t pte)
338 {
339 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
340 }
341
342 static inline pte_t pte_swp_mkexclusive(pte_t pte)
343 {
344 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
345 return pte;
346 }
347
348 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
349 {
350 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
351 return pte;
352 }
353
354 #define pte_ERROR(e) \
355 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
356 #define pmd_ERROR(e) \
357 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
358 #define pgd_ERROR(e) \
359 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
360
361 extern void paging_init(void);
362
363 /* We have our own get_unmapped_area to cope with ADDR_LIMIT_32BIT. */
364 #define HAVE_ARCH_UNMAPPED_AREA
365
366 #endif /* _ALPHA_PGTABLE_H */
367
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.