1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
4 */
5 /dts-v1/;
6
7 /include/ "skeleton.dtsi"
8
9 / {
10 model = "snps,nsim";
11 compatible = "snps,nsim";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&core_intc>;
15
16 chosen {
17 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signals=1";
18 };
19
20 aliases {
21 serial0 = &uart0;
22 };
23
24 fpga {
25 compatible = "simple-bus";
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 /* child and parent address space 1:1 mapped */
30 ranges;
31
32 core_clk: core_clk {
33 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 clock-frequency = <80000000>;
36 };
37
38 core_intc: interrupt-controller {
39 compatible = "snps,arc700-intc";
40 interrupt-controller;
41 #interrupt-cells = <1>;
42 };
43
44 uart0: serial@f0000000 {
45 compatible = "ns16550a";
46 reg = <0xf0000000 0x2000>;
47 interrupts = <24>;
48 clock-frequency = <50000000>;
49 baud = <115200>;
50 reg-shift = <2>;
51 reg-io-width = <4>;
52 no-loopback-test = <1>;
53 };
54
55 arcpct0: pct {
56 compatible = "snps,arc700-pct";
57 };
58 };
59 };
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