1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
4 */
5 /dts-v1/;
6
7 /include/ "skeleton.dtsi"
8
9 / {
10 model = "snps,nsimosci";
11 compatible = "snps,nsimosci";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&core_intc>;
15
16 chosen {
17 /* this is for console on PGU */
18 /* bootargs = "console=tty0 consoleblank=0"; */
19 /* this is for console on serial */
20 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
21 };
22
23 aliases {
24 serial0 = &uart0;
25 };
26
27 fpga {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 /* child and parent address space 1:1 mapped */
33 ranges;
34
35 core_clk: core_clk {
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <20000000>;
39 };
40
41 core_intc: interrupt-controller {
42 compatible = "snps,arc700-intc";
43 interrupt-controller;
44 #interrupt-cells = <1>;
45 };
46
47 uart0: serial@f0000000 {
48 compatible = "ns8250";
49 reg = <0xf0000000 0x2000>;
50 interrupts = <11>;
51 clock-frequency = <3686400>;
52 baud = <115200>;
53 reg-shift = <2>;
54 reg-io-width = <4>;
55 no-loopback-test = <1>;
56 };
57
58 pguclk: pguclk {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <25175000>;
62 };
63
64 pgu@f9000000 {
65 compatible = "snps,arcpgu";
66 reg = <0xf9000000 0x400>;
67 clocks = <&pguclk>;
68 clock-names = "pxlclk";
69 };
70
71 ps2: ps2@f9001000 {
72 compatible = "snps,arc_ps2";
73 reg = <0xf9000400 0x14>;
74 interrupts = <13>;
75 interrupt-names = "arc_ps2_irq";
76 };
77
78 eth0: ethernet@f0003000 {
79 compatible = "ezchip,nps-mgt-enet";
80 reg = <0xf0003000 0x44>;
81 interrupts = <7>;
82 };
83
84 arcpct0: pct {
85 compatible = "snps,arc700-pct";
86 };
87 };
88 };
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