1 # SPDX-License-Identifier: GPL-2.0
2 config ARM
3 bool
4 default y
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CPU_CACHE_ALIASING
9 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
10 select ARCH_HAS_CURRENT_STACK_POINTER
11 select ARCH_HAS_DEBUG_VIRTUAL if MMU
12 select ARCH_HAS_DMA_ALLOC if MMU
13 select ARCH_HAS_DMA_OPS
14 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FORTIFY_SOURCE
17 select ARCH_HAS_KEEPINITRD
18 select ARCH_HAS_KCOV
19 select ARCH_HAS_MEMBARRIER_SYNC_CORE
20 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
21 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
22 select ARCH_HAS_SETUP_DMA_OPS
23 select ARCH_HAS_SET_MEMORY
24 select ARCH_STACKWALK
25 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
26 select ARCH_HAS_STRICT_MODULE_RWX if MMU
27 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
28 select ARCH_HAS_SYNC_DMA_FOR_CPU
29 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
30 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
31 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
32 select ARCH_HAS_GCOV_PROFILE_ALL
33 select ARCH_KEEP_MEMBLOCK
34 select ARCH_HAS_UBSAN
35 select ARCH_MIGHT_HAVE_PC_PARPORT
36 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
37 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
38 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6
39 select ARCH_SUPPORTS_ATOMIC_RMW
40 select ARCH_SUPPORTS_CFI_CLANG
41 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
42 select ARCH_SUPPORTS_PER_VMA_LOCK
43 select ARCH_USE_BUILTIN_BSWAP
44 select ARCH_USE_CMPXCHG_LOCKREF
45 select ARCH_USE_MEMTEST
46 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
47 select ARCH_WANT_GENERAL_HUGETLB
48 select ARCH_WANT_IPC_PARSE_VERSION
49 select ARCH_WANT_LD_ORPHAN_WARN
50 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
51 select BUILDTIME_TABLE_SORT if MMU
52 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
53 select CLONE_BACKWARDS
54 select CPU_PM if SUSPEND || CPU_IDLE
55 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
56 select DMA_DECLARE_COHERENT
57 select DMA_GLOBAL_POOL if !MMU
58 select DMA_NONCOHERENT_MMAP if MMU
59 select EDAC_SUPPORT
60 select EDAC_ATOMIC_SCRUB
61 select GENERIC_ALLOCATOR
62 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
63 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
64 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
65 select GENERIC_IRQ_IPI if SMP
66 select GENERIC_CPU_AUTOPROBE
67 select GENERIC_CPU_DEVICES
68 select GENERIC_EARLY_IOREMAP
69 select GENERIC_IDLE_POLL_SETUP
70 select GENERIC_IRQ_MULTI_HANDLER
71 select GENERIC_IRQ_PROBE
72 select GENERIC_IRQ_SHOW
73 select GENERIC_IRQ_SHOW_LEVEL
74 select GENERIC_LIB_DEVMEM_IS_ALLOWED
75 select GENERIC_PCI_IOMAP
76 select GENERIC_SCHED_CLOCK
77 select GENERIC_SMP_IDLE_THREAD
78 select HARDIRQS_SW_RESEND
79 select HAS_IOPORT
80 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
81 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
82 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
83 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
84 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
85 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
86 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
87 select HAVE_ARCH_MMAP_RND_BITS if MMU
88 select HAVE_ARCH_PFN_VALID
89 select HAVE_ARCH_SECCOMP
90 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
91 select HAVE_ARCH_STACKLEAK
92 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
93 select HAVE_ARCH_TRACEHOOK
94 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
95 select HAVE_ARM_SMCCC if CPU_V7
96 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
97 select HAVE_CONTEXT_TRACKING_USER
98 select HAVE_C_RECORDMCOUNT
99 select HAVE_BUILDTIME_MCOUNT_SORT
100 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
101 select HAVE_DMA_CONTIGUOUS if MMU
102 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
103 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
104 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
105 select HAVE_EXIT_THREAD
106 select HAVE_GUP_FAST if ARM_LPAE
107 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
108 select HAVE_FUNCTION_ERROR_INJECTION
109 select HAVE_FUNCTION_GRAPH_TRACER
110 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
111 select HAVE_GCC_PLUGINS
112 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
113 select HAVE_IRQ_TIME_ACCOUNTING
114 select HAVE_KERNEL_GZIP
115 select HAVE_KERNEL_LZ4
116 select HAVE_KERNEL_LZMA
117 select HAVE_KERNEL_LZO
118 select HAVE_KERNEL_XZ
119 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
120 select HAVE_KRETPROBES if HAVE_KPROBES
121 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD)
122 select HAVE_MOD_ARCH_SPECIFIC
123 select HAVE_NMI
124 select HAVE_OPTPROBES if !THUMB2_KERNEL
125 select HAVE_PAGE_SIZE_4KB
126 select HAVE_PCI if MMU
127 select HAVE_PERF_EVENTS
128 select HAVE_PERF_REGS
129 select HAVE_PERF_USER_STACK_DUMP
130 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
131 select HAVE_REGS_AND_STACK_ACCESS_API
132 select HAVE_RSEQ
133 select HAVE_STACKPROTECTOR
134 select HAVE_SYSCALL_TRACEPOINTS
135 select HAVE_UID16
136 select HAVE_VIRT_CPU_ACCOUNTING_GEN
137 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
138 select IRQ_FORCED_THREADING
139 select LOCK_MM_AND_FIND_VMA
140 select MODULES_USE_ELF_REL
141 select NEED_DMA_MAP_STATE
142 select OF_EARLY_FLATTREE if OF
143 select OLD_SIGACTION
144 select OLD_SIGSUSPEND3
145 select PCI_DOMAINS_GENERIC if PCI
146 select PCI_SYSCALL if PCI
147 select PERF_USE_VMALLOC
148 select RTC_LIB
149 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
150 select SYS_SUPPORTS_APM_EMULATION
151 select THREAD_INFO_IN_TASK
152 select TIMER_OF if OF
153 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
154 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
155 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
156 # Above selects are sorted alphabetically; please add new ones
157 # according to that. Thanks.
158 help
159 The ARM series is a line of low-power-consumption RISC chip designs
160 licensed by ARM Ltd and targeted at embedded applications and
161 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
162 manufactured, but legacy ARM-based PC hardware remains popular in
163 Europe. There is an ARM Linux project with a web page at
164 <http://www.arm.linux.org.uk/>.
165
166 config ARM_HAS_GROUP_RELOCS
167 def_bool y
168 depends on !LD_IS_LLD || LLD_VERSION >= 140000
169 depends on !COMPILE_TEST
170 help
171 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
172 relocations, which have been around for a long time, but were not
173 supported in LLD until version 14. The combined range is -/+ 256 MiB,
174 which is usually sufficient, but not for allyesconfig, so we disable
175 this feature when doing compile testing.
176
177 config ARM_DMA_USE_IOMMU
178 bool
179 select NEED_SG_DMA_LENGTH
180
181 if ARM_DMA_USE_IOMMU
182
183 config ARM_DMA_IOMMU_ALIGNMENT
184 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
185 range 4 9
186 default 8
187 help
188 DMA mapping framework by default aligns all buffers to the smallest
189 PAGE_SIZE order which is greater than or equal to the requested buffer
190 size. This works well for buffers up to a few hundreds kilobytes, but
191 for larger buffers it just a waste of address space. Drivers which has
192 relatively small addressing window (like 64Mib) might run out of
193 virtual space with just a few allocations.
194
195 With this parameter you can specify the maximum PAGE_SIZE order for
196 DMA IOMMU buffers. Larger buffers will be aligned only to this
197 specified order. The order is expressed as a power of two multiplied
198 by the PAGE_SIZE.
199
200 endif
201
202 config SYS_SUPPORTS_APM_EMULATION
203 bool
204
205 config HAVE_TCM
206 bool
207 select GENERIC_ALLOCATOR
208
209 config HAVE_PROC_CPU
210 bool
211
212 config NO_IOPORT_MAP
213 bool
214
215 config SBUS
216 bool
217
218 config STACKTRACE_SUPPORT
219 bool
220 default y
221
222 config LOCKDEP_SUPPORT
223 bool
224 default y
225
226 config ARCH_HAS_ILOG2_U32
227 bool
228
229 config ARCH_HAS_ILOG2_U64
230 bool
231
232 config ARCH_HAS_BANDGAP
233 bool
234
235 config FIX_EARLYCON_MEM
236 def_bool y if MMU
237
238 config GENERIC_HWEIGHT
239 bool
240 default y
241
242 config GENERIC_CALIBRATE_DELAY
243 bool
244 default y
245
246 config ARCH_MAY_HAVE_PC_FDC
247 bool
248
249 config ARCH_SUPPORTS_UPROBES
250 def_bool y
251
252 config GENERIC_ISA_DMA
253 bool
254
255 config FIQ
256 bool
257
258 config ARCH_MTD_XIP
259 bool
260
261 config ARM_PATCH_PHYS_VIRT
262 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM
263 default y
264 depends on MMU
265 help
266 Patch phys-to-virt and virt-to-phys translation functions at
267 boot and module load time according to the position of the
268 kernel in system memory.
269
270 This can only be used with non-XIP MMU kernels where the base
271 of physical memory is at a 2 MiB boundary.
272
273 Only disable this option if you know that you do not require
274 this feature (eg, building a kernel for a single machine) and
275 you need to shrink the kernel to the minimal size.
276
277 config NEED_MACH_IO_H
278 bool
279 help
280 Select this when mach/io.h is required to provide special
281 definitions for this platform. The need for mach/io.h should
282 be avoided when possible.
283
284 config NEED_MACH_MEMORY_H
285 bool
286 help
287 Select this when mach/memory.h is required to provide special
288 definitions for this platform. The need for mach/memory.h should
289 be avoided when possible.
290
291 config PHYS_OFFSET
292 hex "Physical address of main memory" if MMU
293 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
294 default DRAM_BASE if !MMU
295 default 0x00000000 if ARCH_FOOTBRIDGE
296 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
297 default 0xa0000000 if ARCH_PXA
298 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
299 default 0
300 help
301 Please provide the physical address corresponding to the
302 location of main memory in your system.
303
304 config GENERIC_BUG
305 def_bool y
306 depends on BUG
307
308 config PGTABLE_LEVELS
309 int
310 default 3 if ARM_LPAE
311 default 2
312
313 menu "System Type"
314
315 config MMU
316 bool "MMU-based Paged Memory Management Support"
317 default y
318 help
319 Select if you want MMU-based virtualised addressing space
320 support by paged memory management. If unsure, say 'Y'.
321
322 config ARM_SINGLE_ARMV7M
323 def_bool !MMU
324 select ARM_NVIC
325 select CPU_V7M
326 select NO_IOPORT_MAP
327
328 config ARCH_MMAP_RND_BITS_MIN
329 default 8
330
331 config ARCH_MMAP_RND_BITS_MAX
332 default 14 if PAGE_OFFSET=0x40000000
333 default 15 if PAGE_OFFSET=0x80000000
334 default 16
335
336 config ARCH_MULTIPLATFORM
337 bool "Require kernel to be portable to multiple machines" if EXPERT
338 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
339 default y
340 help
341 In general, all Arm machines can be supported in a single
342 kernel image, covering either Armv4/v5 or Armv6/v7.
343
344 However, some configuration options require hardcoding machine
345 specific physical addresses or enable errata workarounds that may
346 break other machines.
347
348 Selecting N here allows using those options, including
349 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
350
351 source "arch/arm/Kconfig.platforms"
352
353 #
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
355 # Kconfigs may be included either alphabetically (according to the
356 # plat- suffix) or along side the corresponding mach-* source.
357 #
358 source "arch/arm/mach-actions/Kconfig"
359
360 source "arch/arm/mach-alpine/Kconfig"
361
362 source "arch/arm/mach-artpec/Kconfig"
363
364 source "arch/arm/mach-aspeed/Kconfig"
365
366 source "arch/arm/mach-at91/Kconfig"
367
368 source "arch/arm/mach-axxia/Kconfig"
369
370 source "arch/arm/mach-bcm/Kconfig"
371
372 source "arch/arm/mach-berlin/Kconfig"
373
374 source "arch/arm/mach-clps711x/Kconfig"
375
376 source "arch/arm/mach-davinci/Kconfig"
377
378 source "arch/arm/mach-digicolor/Kconfig"
379
380 source "arch/arm/mach-dove/Kconfig"
381
382 source "arch/arm/mach-ep93xx/Kconfig"
383
384 source "arch/arm/mach-exynos/Kconfig"
385
386 source "arch/arm/mach-footbridge/Kconfig"
387
388 source "arch/arm/mach-gemini/Kconfig"
389
390 source "arch/arm/mach-highbank/Kconfig"
391
392 source "arch/arm/mach-hisi/Kconfig"
393
394 source "arch/arm/mach-hpe/Kconfig"
395
396 source "arch/arm/mach-imx/Kconfig"
397
398 source "arch/arm/mach-ixp4xx/Kconfig"
399
400 source "arch/arm/mach-keystone/Kconfig"
401
402 source "arch/arm/mach-lpc32xx/Kconfig"
403
404 source "arch/arm/mach-mediatek/Kconfig"
405
406 source "arch/arm/mach-meson/Kconfig"
407
408 source "arch/arm/mach-milbeaut/Kconfig"
409
410 source "arch/arm/mach-mmp/Kconfig"
411
412 source "arch/arm/mach-mstar/Kconfig"
413
414 source "arch/arm/mach-mv78xx0/Kconfig"
415
416 source "arch/arm/mach-mvebu/Kconfig"
417
418 source "arch/arm/mach-mxs/Kconfig"
419
420 source "arch/arm/mach-nomadik/Kconfig"
421
422 source "arch/arm/mach-npcm/Kconfig"
423
424 source "arch/arm/mach-omap1/Kconfig"
425
426 source "arch/arm/mach-omap2/Kconfig"
427
428 source "arch/arm/mach-orion5x/Kconfig"
429
430 source "arch/arm/mach-pxa/Kconfig"
431
432 source "arch/arm/mach-qcom/Kconfig"
433
434 source "arch/arm/mach-realtek/Kconfig"
435
436 source "arch/arm/mach-rpc/Kconfig"
437
438 source "arch/arm/mach-rockchip/Kconfig"
439
440 source "arch/arm/mach-s3c/Kconfig"
441
442 source "arch/arm/mach-s5pv210/Kconfig"
443
444 source "arch/arm/mach-sa1100/Kconfig"
445
446 source "arch/arm/mach-shmobile/Kconfig"
447
448 source "arch/arm/mach-socfpga/Kconfig"
449
450 source "arch/arm/mach-spear/Kconfig"
451
452 source "arch/arm/mach-sti/Kconfig"
453
454 source "arch/arm/mach-stm32/Kconfig"
455
456 source "arch/arm/mach-sunxi/Kconfig"
457
458 source "arch/arm/mach-tegra/Kconfig"
459
460 source "arch/arm/mach-ux500/Kconfig"
461
462 source "arch/arm/mach-versatile/Kconfig"
463
464 source "arch/arm/mach-vt8500/Kconfig"
465
466 source "arch/arm/mach-zynq/Kconfig"
467
468 # ARMv7-M architecture
469 config ARCH_LPC18XX
470 bool "NXP LPC18xx/LPC43xx"
471 depends on ARM_SINGLE_ARMV7M
472 select ARCH_HAS_RESET_CONTROLLER
473 select ARM_AMBA
474 select CLKSRC_LPC32XX
475 select PINCTRL
476 help
477 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
478 high performance microcontrollers.
479
480 config ARCH_MPS2
481 bool "ARM MPS2 platform"
482 depends on ARM_SINGLE_ARMV7M
483 select ARM_AMBA
484 select CLKSRC_MPS2
485 help
486 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
487 with a range of available cores like Cortex-M3/M4/M7.
488
489 Please, note that depends which Application Note is used memory map
490 for the platform may vary, so adjustment of RAM base might be needed.
491
492 # Definitions to make life easier
493 config ARCH_ACORN
494 bool
495
496 config PLAT_ORION
497 bool
498 select CLKSRC_MMIO
499 select GENERIC_IRQ_CHIP
500 select IRQ_DOMAIN
501
502 config PLAT_ORION_LEGACY
503 bool
504 select PLAT_ORION
505
506 config PLAT_VERSATILE
507 bool
508
509 source "arch/arm/mm/Kconfig"
510
511 config IWMMXT
512 bool "Enable iWMMXt support"
513 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
514 default y if PXA27x || PXA3xx || ARCH_MMP
515 help
516 Enable support for iWMMXt context switching at run time if
517 running on a CPU that supports it.
518
519 if !MMU
520 source "arch/arm/Kconfig-nommu"
521 endif
522
523 config PJ4B_ERRATA_4742
524 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
525 depends on CPU_PJ4B && MACH_ARMADA_370
526 default y
527 help
528 When coming out of either a Wait for Interrupt (WFI) or a Wait for
529 Event (WFE) IDLE states, a specific timing sensitivity exists between
530 the retiring WFI/WFE instructions and the newly issued subsequent
531 instructions. This sensitivity can result in a CPU hang scenario.
532 Workaround:
533 The software must insert either a Data Synchronization Barrier (DSB)
534 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
535 instruction
536
537 config ARM_ERRATA_326103
538 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
539 depends on CPU_V6
540 help
541 Executing a SWP instruction to read-only memory does not set bit 11
542 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
543 treat the access as a read, preventing a COW from occurring and
544 causing the faulting task to livelock.
545
546 config ARM_ERRATA_411920
547 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
548 depends on CPU_V6 || CPU_V6K
549 help
550 Invalidation of the Instruction Cache operation can
551 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
552 It does not affect the MPCore. This option enables the ARM Ltd.
553 recommended workaround.
554
555 config ARM_ERRATA_430973
556 bool "ARM errata: Stale prediction on replaced interworking branch"
557 depends on CPU_V7
558 help
559 This option enables the workaround for the 430973 Cortex-A8
560 r1p* erratum. If a code sequence containing an ARM/Thumb
561 interworking branch is replaced with another code sequence at the
562 same virtual address, whether due to self-modifying code or virtual
563 to physical address re-mapping, Cortex-A8 does not recover from the
564 stale interworking branch prediction. This results in Cortex-A8
565 executing the new code sequence in the incorrect ARM or Thumb state.
566 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
567 and also flushes the branch target cache at every context switch.
568 Note that setting specific bits in the ACTLR register may not be
569 available in non-secure mode.
570
571 config ARM_ERRATA_458693
572 bool "ARM errata: Processor deadlock when a false hazard is created"
573 depends on CPU_V7
574 depends on !ARCH_MULTIPLATFORM
575 help
576 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
577 erratum. For very specific sequences of memory operations, it is
578 possible for a hazard condition intended for a cache line to instead
579 be incorrectly associated with a different cache line. This false
580 hazard might then cause a processor deadlock. The workaround enables
581 the L1 caching of the NEON accesses and disables the PLD instruction
582 in the ACTLR register. Note that setting specific bits in the ACTLR
583 register may not be available in non-secure mode and thus is not
584 available on a multiplatform kernel. This should be applied by the
585 bootloader instead.
586
587 config ARM_ERRATA_460075
588 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
589 depends on CPU_V7
590 depends on !ARCH_MULTIPLATFORM
591 help
592 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
593 erratum. Any asynchronous access to the L2 cache may encounter a
594 situation in which recent store transactions to the L2 cache are lost
595 and overwritten with stale memory contents from external memory. The
596 workaround disables the write-allocate mode for the L2 cache via the
597 ACTLR register. Note that setting specific bits in the ACTLR register
598 may not be available in non-secure mode and thus is not available on
599 a multiplatform kernel. This should be applied by the bootloader
600 instead.
601
602 config ARM_ERRATA_742230
603 bool "ARM errata: DMB operation may be faulty"
604 depends on CPU_V7 && SMP
605 depends on !ARCH_MULTIPLATFORM
606 help
607 This option enables the workaround for the 742230 Cortex-A9
608 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
609 between two write operations may not ensure the correct visibility
610 ordering of the two writes. This workaround sets a specific bit in
611 the diagnostic register of the Cortex-A9 which causes the DMB
612 instruction to behave as a DSB, ensuring the correct behaviour of
613 the two writes. Note that setting specific bits in the diagnostics
614 register may not be available in non-secure mode and thus is not
615 available on a multiplatform kernel. This should be applied by the
616 bootloader instead.
617
618 config ARM_ERRATA_742231
619 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
620 depends on CPU_V7 && SMP
621 depends on !ARCH_MULTIPLATFORM
622 help
623 This option enables the workaround for the 742231 Cortex-A9
624 (r2p0..r2p2) erratum. Under certain conditions, specific to the
625 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
626 accessing some data located in the same cache line, may get corrupted
627 data due to bad handling of the address hazard when the line gets
628 replaced from one of the CPUs at the same time as another CPU is
629 accessing it. This workaround sets specific bits in the diagnostic
630 register of the Cortex-A9 which reduces the linefill issuing
631 capabilities of the processor. Note that setting specific bits in the
632 diagnostics register may not be available in non-secure mode and thus
633 is not available on a multiplatform kernel. This should be applied by
634 the bootloader instead.
635
636 config ARM_ERRATA_643719
637 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
638 depends on CPU_V7 && SMP
639 default y
640 help
641 This option enables the workaround for the 643719 Cortex-A9 (prior to
642 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
643 register returns zero when it should return one. The workaround
644 corrects this value, ensuring cache maintenance operations which use
645 it behave as intended and avoiding data corruption.
646
647 config ARM_ERRATA_720789
648 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
649 depends on CPU_V7
650 help
651 This option enables the workaround for the 720789 Cortex-A9 (prior to
652 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
653 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
654 As a consequence of this erratum, some TLB entries which should be
655 invalidated are not, resulting in an incoherency in the system page
656 tables. The workaround changes the TLB flushing routines to invalidate
657 entries regardless of the ASID.
658
659 config ARM_ERRATA_743622
660 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
661 depends on CPU_V7
662 depends on !ARCH_MULTIPLATFORM
663 help
664 This option enables the workaround for the 743622 Cortex-A9
665 (r2p*) erratum. Under very rare conditions, a faulty
666 optimisation in the Cortex-A9 Store Buffer may lead to data
667 corruption. This workaround sets a specific bit in the diagnostic
668 register of the Cortex-A9 which disables the Store Buffer
669 optimisation, preventing the defect from occurring. This has no
670 visible impact on the overall performance or power consumption of the
671 processor. Note that setting specific bits in the diagnostics register
672 may not be available in non-secure mode and thus is not available on a
673 multiplatform kernel. This should be applied by the bootloader instead.
674
675 config ARM_ERRATA_751472
676 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
677 depends on CPU_V7
678 depends on !ARCH_MULTIPLATFORM
679 help
680 This option enables the workaround for the 751472 Cortex-A9 (prior
681 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
682 completion of a following broadcasted operation if the second
683 operation is received by a CPU before the ICIALLUIS has completed,
684 potentially leading to corrupted entries in the cache or TLB.
685 Note that setting specific bits in the diagnostics register may
686 not be available in non-secure mode and thus is not available on
687 a multiplatform kernel. This should be applied by the bootloader
688 instead.
689
690 config ARM_ERRATA_754322
691 bool "ARM errata: possible faulty MMU translations following an ASID switch"
692 depends on CPU_V7
693 help
694 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
695 r3p*) erratum. A speculative memory access may cause a page table walk
696 which starts prior to an ASID switch but completes afterwards. This
697 can populate the micro-TLB with a stale entry which may be hit with
698 the new ASID. This workaround places two dsb instructions in the mm
699 switching code so that no page table walks can cross the ASID switch.
700
701 config ARM_ERRATA_754327
702 bool "ARM errata: no automatic Store Buffer drain"
703 depends on CPU_V7 && SMP
704 help
705 This option enables the workaround for the 754327 Cortex-A9 (prior to
706 r2p0) erratum. The Store Buffer does not have any automatic draining
707 mechanism and therefore a livelock may occur if an external agent
708 continuously polls a memory location waiting to observe an update.
709 This workaround defines cpu_relax() as smp_mb(), preventing correctly
710 written polling loops from denying visibility of updates to memory.
711
712 config ARM_ERRATA_364296
713 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
714 depends on CPU_V6
715 help
716 This options enables the workaround for the 364296 ARM1136
717 r0p2 erratum (possible cache data corruption with
718 hit-under-miss enabled). It sets the undocumented bit 31 in
719 the auxiliary control register and the FI bit in the control
720 register, thus disabling hit-under-miss without putting the
721 processor into full low interrupt latency mode. ARM11MPCore
722 is not affected.
723
724 config ARM_ERRATA_764369
725 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
726 depends on CPU_V7 && SMP
727 help
728 This option enables the workaround for erratum 764369
729 affecting Cortex-A9 MPCore with two or more processors (all
730 current revisions). Under certain timing circumstances, a data
731 cache line maintenance operation by MVA targeting an Inner
732 Shareable memory region may fail to proceed up to either the
733 Point of Coherency or to the Point of Unification of the
734 system. This workaround adds a DSB instruction before the
735 relevant cache maintenance functions and sets a specific bit
736 in the diagnostic control register of the SCU.
737
738 config ARM_ERRATA_764319
739 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
740 depends on CPU_V7
741 help
742 This option enables the workaround for the 764319 Cortex-A9 erratum.
743 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
744 unexpected Undefined Instruction exception when the DBGSWENABLE
745 external pin is set to 0, even when the CP14 accesses are performed
746 from a privileged mode. This work around catches the exception in a
747 way the kernel does not stop execution.
748
749 config ARM_ERRATA_775420
750 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
751 depends on CPU_V7
752 help
753 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
754 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
755 operation aborts with MMU exception, it might cause the processor
756 to deadlock. This workaround puts DSB before executing ISB if
757 an abort may occur on cache maintenance.
758
759 config ARM_ERRATA_798181
760 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
761 depends on CPU_V7 && SMP
762 help
763 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
764 adequately shooting down all use of the old entries. This
765 option enables the Linux kernel workaround for this erratum
766 which sends an IPI to the CPUs that are running the same ASID
767 as the one being invalidated.
768
769 config ARM_ERRATA_773022
770 bool "ARM errata: incorrect instructions may be executed from loop buffer"
771 depends on CPU_V7
772 help
773 This option enables the workaround for the 773022 Cortex-A15
774 (up to r0p4) erratum. In certain rare sequences of code, the
775 loop buffer may deliver incorrect instructions. This
776 workaround disables the loop buffer to avoid the erratum.
777
778 config ARM_ERRATA_818325_852422
779 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
780 depends on CPU_V7
781 help
782 This option enables the workaround for:
783 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
784 instruction might deadlock. Fixed in r0p1.
785 - Cortex-A12 852422: Execution of a sequence of instructions might
786 lead to either a data corruption or a CPU deadlock. Not fixed in
787 any Cortex-A12 cores yet.
788 This workaround for all both errata involves setting bit[12] of the
789 Feature Register. This bit disables an optimisation applied to a
790 sequence of 2 instructions that use opposing condition codes.
791
792 config ARM_ERRATA_821420
793 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
794 depends on CPU_V7
795 help
796 This option enables the workaround for the 821420 Cortex-A12
797 (all revs) erratum. In very rare timing conditions, a sequence
798 of VMOV to Core registers instructions, for which the second
799 one is in the shadow of a branch or abort, can lead to a
800 deadlock when the VMOV instructions are issued out-of-order.
801
802 config ARM_ERRATA_825619
803 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
804 depends on CPU_V7
805 help
806 This option enables the workaround for the 825619 Cortex-A12
807 (all revs) erratum. Within rare timing constraints, executing a
808 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
809 and Device/Strongly-Ordered loads and stores might cause deadlock
810
811 config ARM_ERRATA_857271
812 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
813 depends on CPU_V7
814 help
815 This option enables the workaround for the 857271 Cortex-A12
816 (all revs) erratum. Under very rare timing conditions, the CPU might
817 hang. The workaround is expected to have a < 1% performance impact.
818
819 config ARM_ERRATA_852421
820 bool "ARM errata: A17: DMB ST might fail to create order between stores"
821 depends on CPU_V7
822 help
823 This option enables the workaround for the 852421 Cortex-A17
824 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
825 execution of a DMB ST instruction might fail to properly order
826 stores from GroupA and stores from GroupB.
827
828 config ARM_ERRATA_852423
829 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
830 depends on CPU_V7
831 help
832 This option enables the workaround for:
833 - Cortex-A17 852423: Execution of a sequence of instructions might
834 lead to either a data corruption or a CPU deadlock. Not fixed in
835 any Cortex-A17 cores yet.
836 This is identical to Cortex-A12 erratum 852422. It is a separate
837 config option from the A12 erratum due to the way errata are checked
838 for and handled.
839
840 config ARM_ERRATA_857272
841 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
842 depends on CPU_V7
843 help
844 This option enables the workaround for the 857272 Cortex-A17 erratum.
845 This erratum is not known to be fixed in any A17 revision.
846 This is identical to Cortex-A12 erratum 857271. It is a separate
847 config option from the A12 erratum due to the way errata are checked
848 for and handled.
849
850 endmenu
851
852 source "arch/arm/common/Kconfig"
853
854 menu "Bus support"
855
856 config ISA
857 bool
858 help
859 Find out whether you have ISA slots on your motherboard. ISA is the
860 name of a bus system, i.e. the way the CPU talks to the other stuff
861 inside your box. Other bus systems are PCI, EISA, MicroChannel
862 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
863 newer boards don't support it. If you have ISA, say Y, otherwise N.
864
865 # Select ISA DMA interface
866 config ISA_DMA_API
867 bool
868
869 config ARM_ERRATA_814220
870 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
871 depends on CPU_V7
872 help
873 The v7 ARM states that all cache and branch predictor maintenance
874 operations that do not specify an address execute, relative to
875 each other, in program order.
876 However, because of this erratum, an L2 set/way cache maintenance
877 operation can overtake an L1 set/way cache maintenance operation.
878 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
879 r0p4, r0p5.
880
881 endmenu
882
883 menu "Kernel Features"
884
885 config HAVE_SMP
886 bool
887 help
888 This option should be selected by machines which have an SMP-
889 capable CPU.
890
891 The only effect of this option is to make the SMP-related
892 options available to the user for configuration.
893
894 config SMP
895 bool "Symmetric Multi-Processing"
896 depends on CPU_V6K || CPU_V7
897 depends on HAVE_SMP
898 depends on MMU || ARM_MPU
899 select IRQ_WORK
900 help
901 This enables support for systems with more than one CPU. If you have
902 a system with only one CPU, say N. If you have a system with more
903 than one CPU, say Y.
904
905 If you say N here, the kernel will run on uni- and multiprocessor
906 machines, but will use only one CPU of a multiprocessor machine. If
907 you say Y here, the kernel will run on many, but not all,
908 uniprocessor machines. On a uniprocessor machine, the kernel
909 will run faster if you say N here.
910
911 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
912 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
913 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
914
915 If you don't know what to do here, say N.
916
917 config SMP_ON_UP
918 bool "Allow booting SMP kernel on uniprocessor systems"
919 depends on SMP && MMU
920 default y
921 help
922 SMP kernels contain instructions which fail on non-SMP processors.
923 Enabling this option allows the kernel to modify itself to make
924 these instructions safe. Disabling it allows about 1K of space
925 savings.
926
927 If you don't know what to do here, say Y.
928
929
930 config CURRENT_POINTER_IN_TPIDRURO
931 def_bool y
932 depends on CPU_32v6K && !CPU_V6
933
934 config IRQSTACKS
935 def_bool y
936 select HAVE_IRQ_EXIT_ON_IRQ_STACK
937 select HAVE_SOFTIRQ_ON_OWN_STACK
938
939 config ARM_CPU_TOPOLOGY
940 bool "Support cpu topology definition"
941 depends on SMP && CPU_V7
942 default y
943 help
944 Support ARM cpu topology definition. The MPIDR register defines
945 affinity between processors which is then used to describe the cpu
946 topology of an ARM System.
947
948 config SCHED_MC
949 bool "Multi-core scheduler support"
950 depends on ARM_CPU_TOPOLOGY
951 help
952 Multi-core scheduler support improves the CPU scheduler's decision
953 making when dealing with multi-core CPU chips at a cost of slightly
954 increased overhead in some places. If unsure say N here.
955
956 config SCHED_SMT
957 bool "SMT scheduler support"
958 depends on ARM_CPU_TOPOLOGY
959 help
960 Improves the CPU scheduler's decision making when dealing with
961 MultiThreading at a cost of slightly increased overhead in some
962 places. If unsure say N here.
963
964 config HAVE_ARM_SCU
965 bool
966 help
967 This option enables support for the ARM snoop control unit
968
969 config HAVE_ARM_ARCH_TIMER
970 bool "Architected timer support"
971 depends on CPU_V7
972 select ARM_ARCH_TIMER
973 help
974 This option enables support for the ARM architected timer
975
976 config HAVE_ARM_TWD
977 bool
978 help
979 This options enables support for the ARM timer and watchdog unit
980
981 config MCPM
982 bool "Multi-Cluster Power Management"
983 depends on CPU_V7 && SMP
984 help
985 This option provides the common power management infrastructure
986 for (multi-)cluster based systems, such as big.LITTLE based
987 systems.
988
989 config MCPM_QUAD_CLUSTER
990 bool
991 depends on MCPM
992 help
993 To avoid wasting resources unnecessarily, MCPM only supports up
994 to 2 clusters by default.
995 Platforms with 3 or 4 clusters that use MCPM must select this
996 option to allow the additional clusters to be managed.
997
998 config BIG_LITTLE
999 bool "big.LITTLE support (Experimental)"
1000 depends on CPU_V7 && SMP
1001 select MCPM
1002 help
1003 This option enables support selections for the big.LITTLE
1004 system architecture.
1005
1006 config BL_SWITCHER
1007 bool "big.LITTLE switcher support"
1008 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1009 select CPU_PM
1010 help
1011 The big.LITTLE "switcher" provides the core functionality to
1012 transparently handle transition between a cluster of A15's
1013 and a cluster of A7's in a big.LITTLE system.
1014
1015 config BL_SWITCHER_DUMMY_IF
1016 tristate "Simple big.LITTLE switcher user interface"
1017 depends on BL_SWITCHER && DEBUG_KERNEL
1018 help
1019 This is a simple and dummy char dev interface to control
1020 the big.LITTLE switcher core code. It is meant for
1021 debugging purposes only.
1022
1023 choice
1024 prompt "Memory split"
1025 depends on MMU
1026 default VMSPLIT_3G
1027 help
1028 Select the desired split between kernel and user memory.
1029
1030 If you are not absolutely sure what you are doing, leave this
1031 option alone!
1032
1033 config VMSPLIT_3G
1034 bool "3G/1G user/kernel split"
1035 config VMSPLIT_3G_OPT
1036 depends on !ARM_LPAE
1037 bool "3G/1G user/kernel split (for full 1G low memory)"
1038 config VMSPLIT_2G
1039 bool "2G/2G user/kernel split"
1040 config VMSPLIT_1G
1041 bool "1G/3G user/kernel split"
1042 endchoice
1043
1044 config PAGE_OFFSET
1045 hex
1046 default PHYS_OFFSET if !MMU
1047 default 0x40000000 if VMSPLIT_1G
1048 default 0x80000000 if VMSPLIT_2G
1049 default 0xB0000000 if VMSPLIT_3G_OPT
1050 default 0xC0000000
1051
1052 config KASAN_SHADOW_OFFSET
1053 hex
1054 depends on KASAN
1055 default 0x1f000000 if PAGE_OFFSET=0x40000000
1056 default 0x5f000000 if PAGE_OFFSET=0x80000000
1057 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1058 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1059 default 0xffffffff
1060
1061 config NR_CPUS
1062 int "Maximum number of CPUs (2-32)"
1063 range 2 16 if DEBUG_KMAP_LOCAL
1064 range 2 32 if !DEBUG_KMAP_LOCAL
1065 depends on SMP
1066 default "4"
1067 help
1068 The maximum number of CPUs that the kernel can support.
1069 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1070 debugging is enabled, which uses half of the per-CPU fixmap
1071 slots as guard regions.
1072
1073 config HOTPLUG_CPU
1074 bool "Support for hot-pluggable CPUs"
1075 depends on SMP
1076 select GENERIC_IRQ_MIGRATION
1077 help
1078 Say Y here to experiment with turning CPUs off and on. CPUs
1079 can be controlled through /sys/devices/system/cpu.
1080
1081 config ARM_PSCI
1082 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1083 depends on HAVE_ARM_SMCCC
1084 select ARM_PSCI_FW
1085 help
1086 Say Y here if you want Linux to communicate with system firmware
1087 implementing the PSCI specification for CPU-centric power
1088 management operations described in ARM document number ARM DEN
1089 0022A ("Power State Coordination Interface System Software on
1090 ARM processors").
1091
1092 config HZ_FIXED
1093 int
1094 default 128 if SOC_AT91RM9200
1095 default 0
1096
1097 choice
1098 depends on HZ_FIXED = 0
1099 prompt "Timer frequency"
1100
1101 config HZ_100
1102 bool "100 Hz"
1103
1104 config HZ_200
1105 bool "200 Hz"
1106
1107 config HZ_250
1108 bool "250 Hz"
1109
1110 config HZ_300
1111 bool "300 Hz"
1112
1113 config HZ_500
1114 bool "500 Hz"
1115
1116 config HZ_1000
1117 bool "1000 Hz"
1118
1119 endchoice
1120
1121 config HZ
1122 int
1123 default HZ_FIXED if HZ_FIXED != 0
1124 default 100 if HZ_100
1125 default 200 if HZ_200
1126 default 250 if HZ_250
1127 default 300 if HZ_300
1128 default 500 if HZ_500
1129 default 1000
1130
1131 config SCHED_HRTICK
1132 def_bool HIGH_RES_TIMERS
1133
1134 config THUMB2_KERNEL
1135 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1136 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1137 default y if CPU_THUMBONLY
1138 select ARM_UNWIND
1139 help
1140 By enabling this option, the kernel will be compiled in
1141 Thumb-2 mode.
1142
1143 If unsure, say N.
1144
1145 config ARM_PATCH_IDIV
1146 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1147 depends on CPU_32v7
1148 default y
1149 help
1150 The ARM compiler inserts calls to __aeabi_idiv() and
1151 __aeabi_uidiv() when it needs to perform division on signed
1152 and unsigned integers. Some v7 CPUs have support for the sdiv
1153 and udiv instructions that can be used to implement those
1154 functions.
1155
1156 Enabling this option allows the kernel to modify itself to
1157 replace the first two instructions of these library functions
1158 with the sdiv or udiv plus "bx lr" instructions when the CPU
1159 it is running on supports them. Typically this will be faster
1160 and less power intensive than running the original library
1161 code to do integer division.
1162
1163 config AEABI
1164 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1165 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1166 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1167 help
1168 This option allows for the kernel to be compiled using the latest
1169 ARM ABI (aka EABI). This is only useful if you are using a user
1170 space environment that is also compiled with EABI.
1171
1172 Since there are major incompatibilities between the legacy ABI and
1173 EABI, especially with regard to structure member alignment, this
1174 option also changes the kernel syscall calling convention to
1175 disambiguate both ABIs and allow for backward compatibility support
1176 (selected with CONFIG_OABI_COMPAT).
1177
1178 To use this you need GCC version 4.0.0 or later.
1179
1180 config OABI_COMPAT
1181 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1182 depends on AEABI && !THUMB2_KERNEL
1183 help
1184 This option preserves the old syscall interface along with the
1185 new (ARM EABI) one. It also provides a compatibility layer to
1186 intercept syscalls that have structure arguments which layout
1187 in memory differs between the legacy ABI and the new ARM EABI
1188 (only for non "thumb" binaries). This option adds a tiny
1189 overhead to all syscalls and produces a slightly larger kernel.
1190
1191 The seccomp filter system will not be available when this is
1192 selected, since there is no way yet to sensibly distinguish
1193 between calling conventions during filtering.
1194
1195 If you know you'll be using only pure EABI user space then you
1196 can say N here. If this option is not selected and you attempt
1197 to execute a legacy ABI binary then the result will be
1198 UNPREDICTABLE (in fact it can be predicted that it won't work
1199 at all). If in doubt say N.
1200
1201 config ARCH_SELECT_MEMORY_MODEL
1202 def_bool y
1203
1204 config ARCH_FLATMEM_ENABLE
1205 def_bool !(ARCH_RPC || ARCH_SA1100)
1206
1207 config ARCH_SPARSEMEM_ENABLE
1208 def_bool !ARCH_FOOTBRIDGE
1209 select SPARSEMEM_STATIC if SPARSEMEM
1210
1211 config HIGHMEM
1212 bool "High Memory Support"
1213 depends on MMU
1214 select KMAP_LOCAL
1215 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1216 help
1217 The address space of ARM processors is only 4 Gigabytes large
1218 and it has to accommodate user address space, kernel address
1219 space as well as some memory mapped IO. That means that, if you
1220 have a large amount of physical memory and/or IO, not all of the
1221 memory can be "permanently mapped" by the kernel. The physical
1222 memory that is not permanently mapped is called "high memory".
1223
1224 Depending on the selected kernel/user memory split, minimum
1225 vmalloc space and actual amount of RAM, you may not need this
1226 option which should result in a slightly faster kernel.
1227
1228 If unsure, say n.
1229
1230 config HIGHPTE
1231 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1232 depends on HIGHMEM
1233 default y
1234 help
1235 The VM uses one page of physical memory for each page table.
1236 For systems with a lot of processes, this can use a lot of
1237 precious low memory, eventually leading to low memory being
1238 consumed by page tables. Setting this option will allow
1239 user-space 2nd level page tables to reside in high memory.
1240
1241 config ARM_PAN
1242 bool "Enable privileged no-access"
1243 depends on MMU
1244 default y
1245 help
1246 Increase kernel security by ensuring that normal kernel accesses
1247 are unable to access userspace addresses. This can help prevent
1248 use-after-free bugs becoming an exploitable privilege escalation
1249 by ensuring that magic values (such as LIST_POISON) will always
1250 fault when dereferenced.
1251
1252 The implementation uses CPU domains when !CONFIG_ARM_LPAE and
1253 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE.
1254
1255 config CPU_SW_DOMAIN_PAN
1256 def_bool y
1257 depends on ARM_PAN && !ARM_LPAE
1258 help
1259 Enable use of CPU domains to implement privileged no-access.
1260
1261 CPUs with low-vector mappings use a best-efforts implementation.
1262 Their lower 1MB needs to remain accessible for the vectors, but
1263 the remainder of userspace will become appropriately inaccessible.
1264
1265 config CPU_TTBR0_PAN
1266 def_bool y
1267 depends on ARM_PAN && ARM_LPAE
1268 help
1269 Enable privileged no-access by disabling TTBR0 page table walks when
1270 running in kernel mode.
1271
1272 config HW_PERF_EVENTS
1273 def_bool y
1274 depends on ARM_PMU
1275
1276 config ARM_MODULE_PLTS
1277 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1278 depends on MODULES
1279 select KASAN_VMALLOC if KASAN
1280 default y
1281 help
1282 Allocate PLTs when loading modules so that jumps and calls whose
1283 targets are too far away for their relative offsets to be encoded
1284 in the instructions themselves can be bounced via veneers in the
1285 module's PLT. This allows modules to be allocated in the generic
1286 vmalloc area after the dedicated module memory area has been
1287 exhausted. The modules will use slightly more memory, but after
1288 rounding up to page size, the actual memory footprint is usually
1289 the same.
1290
1291 Disabling this is usually safe for small single-platform
1292 configurations. If unsure, say y.
1293
1294 config ARCH_FORCE_MAX_ORDER
1295 int "Order of maximal physically contiguous allocations"
1296 default "11" if SOC_AM33XX
1297 default "8" if SA1111
1298 default "10"
1299 help
1300 The kernel page allocator limits the size of maximal physically
1301 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1302 defines the maximal power of two of number of pages that can be
1303 allocated as a single contiguous block. This option allows
1304 overriding the default setting when ability to allocate very
1305 large blocks of physically contiguous memory is required.
1306
1307 Don't change if unsure.
1308
1309 config ALIGNMENT_TRAP
1310 def_bool CPU_CP15_MMU
1311 select HAVE_PROC_CPU if PROC_FS
1312 help
1313 ARM processors cannot fetch/store information which is not
1314 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1315 address divisible by 4. On 32-bit ARM processors, these non-aligned
1316 fetch/store instructions will be emulated in software if you say
1317 here, which has a severe performance impact. This is necessary for
1318 correct operation of some network protocols. With an IP-only
1319 configuration it is safe to say N, otherwise say Y.
1320
1321 config UACCESS_WITH_MEMCPY
1322 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1323 depends on MMU
1324 default y if CPU_FEROCEON
1325 help
1326 Implement faster copy_to_user and clear_user methods for CPU
1327 cores where a 8-word STM instruction give significantly higher
1328 memory write throughput than a sequence of individual 32bit stores.
1329
1330 A possible side effect is a slight increase in scheduling latency
1331 between threads sharing the same address space if they invoke
1332 such copy operations with large buffers.
1333
1334 However, if the CPU data cache is using a write-allocate mode,
1335 this option is unlikely to provide any performance gain.
1336
1337 config PARAVIRT
1338 bool "Enable paravirtualization code"
1339 help
1340 This changes the kernel so it can modify itself when it is run
1341 under a hypervisor, potentially improving performance significantly
1342 over full virtualization.
1343
1344 config PARAVIRT_TIME_ACCOUNTING
1345 bool "Paravirtual steal time accounting"
1346 select PARAVIRT
1347 help
1348 Select this option to enable fine granularity task steal time
1349 accounting. Time spent executing other tasks in parallel with
1350 the current vCPU is discounted from the vCPU power. To account for
1351 that, there can be a small performance impact.
1352
1353 If in doubt, say N here.
1354
1355 config XEN_DOM0
1356 def_bool y
1357 depends on XEN
1358
1359 config XEN
1360 bool "Xen guest support on ARM"
1361 depends on ARM && AEABI && OF
1362 depends on CPU_V7 && !CPU_V6
1363 depends on !GENERIC_ATOMIC64
1364 depends on MMU
1365 select ARCH_DMA_ADDR_T_64BIT
1366 select ARM_PSCI
1367 select SWIOTLB
1368 select SWIOTLB_XEN
1369 select PARAVIRT
1370 help
1371 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1372
1373 config CC_HAVE_STACKPROTECTOR_TLS
1374 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1375
1376 config STACKPROTECTOR_PER_TASK
1377 bool "Use a unique stack canary value for each task"
1378 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1379 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1380 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1381 default y
1382 help
1383 Due to the fact that GCC uses an ordinary symbol reference from
1384 which to load the value of the stack canary, this value can only
1385 change at reboot time on SMP systems, and all tasks running in the
1386 kernel's address space are forced to use the same canary value for
1387 the entire duration that the system is up.
1388
1389 Enable this option to switch to a different method that uses a
1390 different canary value for each task.
1391
1392 endmenu
1393
1394 menu "Boot options"
1395
1396 config USE_OF
1397 bool "Flattened Device Tree support"
1398 select IRQ_DOMAIN
1399 select OF
1400 help
1401 Include support for flattened device tree machine descriptions.
1402
1403 config ARCH_WANT_FLAT_DTB_INSTALL
1404 def_bool y
1405
1406 config ATAGS
1407 bool "Support for the traditional ATAGS boot data passing"
1408 default y
1409 help
1410 This is the traditional way of passing data to the kernel at boot
1411 time. If you are solely relying on the flattened device tree (or
1412 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1413 to remove ATAGS support from your kernel binary.
1414
1415 config DEPRECATED_PARAM_STRUCT
1416 bool "Provide old way to pass kernel parameters"
1417 depends on ATAGS
1418 help
1419 This was deprecated in 2001 and announced to live on for 5 years.
1420 Some old boot loaders still use this way.
1421
1422 # Compressed boot loader in ROM. Yes, we really want to ask about
1423 # TEXT and BSS so we preserve their values in the config files.
1424 config ZBOOT_ROM_TEXT
1425 hex "Compressed ROM boot loader base address"
1426 default 0x0
1427 help
1428 The physical address at which the ROM-able zImage is to be
1429 placed in the target. Platforms which normally make use of
1430 ROM-able zImage formats normally set this to a suitable
1431 value in their defconfig file.
1432
1433 If ZBOOT_ROM is not enabled, this has no effect.
1434
1435 config ZBOOT_ROM_BSS
1436 hex "Compressed ROM boot loader BSS address"
1437 default 0x0
1438 help
1439 The base address of an area of read/write memory in the target
1440 for the ROM-able zImage which must be available while the
1441 decompressor is running. It must be large enough to hold the
1442 entire decompressed kernel plus an additional 128 KiB.
1443 Platforms which normally make use of ROM-able zImage formats
1444 normally set this to a suitable value in their defconfig file.
1445
1446 If ZBOOT_ROM is not enabled, this has no effect.
1447
1448 config ZBOOT_ROM
1449 bool "Compressed boot loader in ROM/flash"
1450 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1451 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1452 help
1453 Say Y here if you intend to execute your compressed kernel image
1454 (zImage) directly from ROM or flash. If unsure, say N.
1455
1456 config ARM_APPENDED_DTB
1457 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1458 depends on OF
1459 help
1460 With this option, the boot code will look for a device tree binary
1461 (DTB) appended to zImage
1462 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1463
1464 This is meant as a backward compatibility convenience for those
1465 systems with a bootloader that can't be upgraded to accommodate
1466 the documented boot protocol using a device tree.
1467
1468 Beware that there is very little in terms of protection against
1469 this option being confused by leftover garbage in memory that might
1470 look like a DTB header after a reboot if no actual DTB is appended
1471 to zImage. Do not leave this option active in a production kernel
1472 if you don't intend to always append a DTB. Proper passing of the
1473 location into r2 of a bootloader provided DTB is always preferable
1474 to this option.
1475
1476 config ARM_ATAG_DTB_COMPAT
1477 bool "Supplement the appended DTB with traditional ATAG information"
1478 depends on ARM_APPENDED_DTB
1479 help
1480 Some old bootloaders can't be updated to a DTB capable one, yet
1481 they provide ATAGs with memory configuration, the ramdisk address,
1482 the kernel cmdline string, etc. Such information is dynamically
1483 provided by the bootloader and can't always be stored in a static
1484 DTB. To allow a device tree enabled kernel to be used with such
1485 bootloaders, this option allows zImage to extract the information
1486 from the ATAG list and store it at run time into the appended DTB.
1487
1488 choice
1489 prompt "Kernel command line type"
1490 depends on ARM_ATAG_DTB_COMPAT
1491 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1492
1493 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1494 bool "Use bootloader kernel arguments if available"
1495 help
1496 Uses the command-line options passed by the boot loader instead of
1497 the device tree bootargs property. If the boot loader doesn't provide
1498 any, the device tree bootargs property will be used.
1499
1500 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1501 bool "Extend with bootloader kernel arguments"
1502 help
1503 The command-line arguments provided by the boot loader will be
1504 appended to the the device tree bootargs property.
1505
1506 endchoice
1507
1508 config CMDLINE
1509 string "Default kernel command string"
1510 default ""
1511 help
1512 On some architectures (e.g. CATS), there is currently no way
1513 for the boot loader to pass arguments to the kernel. For these
1514 architectures, you should supply some command-line options at build
1515 time by entering them here. As a minimum, you should specify the
1516 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1517
1518 choice
1519 prompt "Kernel command line type"
1520 depends on CMDLINE != ""
1521 default CMDLINE_FROM_BOOTLOADER
1522
1523 config CMDLINE_FROM_BOOTLOADER
1524 bool "Use bootloader kernel arguments if available"
1525 help
1526 Uses the command-line options passed by the boot loader. If
1527 the boot loader doesn't provide any, the default kernel command
1528 string provided in CMDLINE will be used.
1529
1530 config CMDLINE_EXTEND
1531 bool "Extend bootloader kernel arguments"
1532 help
1533 The command-line arguments provided by the boot loader will be
1534 appended to the default kernel command string.
1535
1536 config CMDLINE_FORCE
1537 bool "Always use the default kernel command string"
1538 help
1539 Always use the default kernel command string, even if the boot
1540 loader passes other arguments to the kernel.
1541 This is useful if you cannot or don't want to change the
1542 command-line options your boot loader passes to the kernel.
1543 endchoice
1544
1545 config XIP_KERNEL
1546 bool "Kernel Execute-In-Place from ROM"
1547 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1548 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
1549 help
1550 Execute-In-Place allows the kernel to run from non-volatile storage
1551 directly addressable by the CPU, such as NOR flash. This saves RAM
1552 space since the text section of the kernel is not loaded from flash
1553 to RAM. Read-write sections, such as the data section and stack,
1554 are still copied to RAM. The XIP kernel is not compressed since
1555 it has to run directly from flash, so it will take more space to
1556 store it. The flash address used to link the kernel object files,
1557 and for storing it, is configuration dependent. Therefore, if you
1558 say Y here, you must know the proper physical address where to
1559 store the kernel image depending on your own flash memory usage.
1560
1561 Also note that the make target becomes "make xipImage" rather than
1562 "make zImage" or "make Image". The final kernel binary to put in
1563 ROM memory will be arch/arm/boot/xipImage.
1564
1565 If unsure, say N.
1566
1567 config XIP_PHYS_ADDR
1568 hex "XIP Kernel Physical Location"
1569 depends on XIP_KERNEL
1570 default "0x00080000"
1571 help
1572 This is the physical address in your flash memory the kernel will
1573 be linked for and stored to. This address is dependent on your
1574 own flash usage.
1575
1576 config XIP_DEFLATED_DATA
1577 bool "Store kernel .data section compressed in ROM"
1578 depends on XIP_KERNEL
1579 select ZLIB_INFLATE
1580 help
1581 Before the kernel is actually executed, its .data section has to be
1582 copied to RAM from ROM. This option allows for storing that data
1583 in compressed form and decompressed to RAM rather than merely being
1584 copied, saving some precious ROM space. A possible drawback is a
1585 slightly longer boot delay.
1586
1587 config ARCH_SUPPORTS_KEXEC
1588 def_bool (!SMP || PM_SLEEP_SMP) && MMU
1589
1590 config ATAGS_PROC
1591 bool "Export atags in procfs"
1592 depends on ATAGS && KEXEC
1593 default y
1594 help
1595 Should the atags used to boot the kernel be exported in an "atags"
1596 file in procfs. Useful with kexec.
1597
1598 config ARCH_SUPPORTS_CRASH_DUMP
1599 def_bool y
1600
1601 config AUTO_ZRELADDR
1602 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
1603 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1604 help
1605 ZRELADDR is the physical address where the decompressed kernel
1606 image will be placed. If AUTO_ZRELADDR is selected, the address
1607 will be determined at run-time, either by masking the current IP
1608 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1609 This assumes the zImage being placed in the first 128MB from
1610 start of memory.
1611
1612 config EFI_STUB
1613 bool
1614
1615 config EFI
1616 bool "UEFI runtime support"
1617 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1618 select UCS2_STRING
1619 select EFI_PARAMS_FROM_FDT
1620 select EFI_STUB
1621 select EFI_GENERIC_STUB
1622 select EFI_RUNTIME_WRAPPERS
1623 help
1624 This option provides support for runtime services provided
1625 by UEFI firmware (such as non-volatile variables, realtime
1626 clock, and platform reset). A UEFI stub is also provided to
1627 allow the kernel to be booted as an EFI application. This
1628 is only useful for kernels that may run on systems that have
1629 UEFI firmware.
1630
1631 config DMI
1632 bool "Enable support for SMBIOS (DMI) tables"
1633 depends on EFI
1634 default y
1635 help
1636 This enables SMBIOS/DMI feature for systems.
1637
1638 This option is only useful on systems that have UEFI firmware.
1639 However, even with this option, the resultant kernel should
1640 continue to boot on existing non-UEFI platforms.
1641
1642 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1643 i.e., the the practice of identifying the platform via DMI to
1644 decide whether certain workarounds for buggy hardware and/or
1645 firmware need to be enabled. This would require the DMI subsystem
1646 to be enabled much earlier than we do on ARM, which is non-trivial.
1647
1648 endmenu
1649
1650 menu "CPU Power Management"
1651
1652 source "drivers/cpufreq/Kconfig"
1653
1654 source "drivers/cpuidle/Kconfig"
1655
1656 endmenu
1657
1658 menu "Floating point emulation"
1659
1660 comment "At least one emulation must be selected"
1661
1662 config FPE_NWFPE
1663 bool "NWFPE math emulation"
1664 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1665 help
1666 Say Y to include the NWFPE floating point emulator in the kernel.
1667 This is necessary to run most binaries. Linux does not currently
1668 support floating point hardware so you need to say Y here even if
1669 your machine has an FPA or floating point co-processor podule.
1670
1671 You may say N here if you are going to load the Acorn FPEmulator
1672 early in the bootup.
1673
1674 config FPE_NWFPE_XP
1675 bool "Support extended precision"
1676 depends on FPE_NWFPE
1677 help
1678 Say Y to include 80-bit support in the kernel floating-point
1679 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1680 Note that gcc does not generate 80-bit operations by default,
1681 so in most cases this option only enlarges the size of the
1682 floating point emulator without any good reason.
1683
1684 You almost surely want to say N here.
1685
1686 config FPE_FASTFPE
1687 bool "FastFPE math emulation (EXPERIMENTAL)"
1688 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1689 help
1690 Say Y here to include the FAST floating point emulator in the kernel.
1691 This is an experimental much faster emulator which now also has full
1692 precision for the mantissa. It does not support any exceptions.
1693 It is very simple, and approximately 3-6 times faster than NWFPE.
1694
1695 It should be sufficient for most programs. It may be not suitable
1696 for scientific calculations, but you have to check this for yourself.
1697 If you do not feel you need a faster FP emulation you should better
1698 choose NWFPE.
1699
1700 config VFP
1701 bool "VFP-format floating point maths"
1702 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1703 help
1704 Say Y to include VFP support code in the kernel. This is needed
1705 if your hardware includes a VFP unit.
1706
1707 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1708 release notes and additional status information.
1709
1710 Say N if your target does not have VFP hardware.
1711
1712 config VFPv3
1713 bool
1714 depends on VFP
1715 default y if CPU_V7
1716
1717 config NEON
1718 bool "Advanced SIMD (NEON) Extension support"
1719 depends on VFPv3 && CPU_V7
1720 help
1721 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1722 Extension.
1723
1724 config KERNEL_MODE_NEON
1725 bool "Support for NEON in kernel mode"
1726 depends on NEON && AEABI
1727 help
1728 Say Y to include support for NEON in kernel mode.
1729
1730 endmenu
1731
1732 menu "Power management options"
1733
1734 source "kernel/power/Kconfig"
1735
1736 config ARCH_SUSPEND_POSSIBLE
1737 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1738 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1739 def_bool y
1740
1741 config ARM_CPU_SUSPEND
1742 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1743 depends on ARCH_SUSPEND_POSSIBLE
1744
1745 config ARCH_HIBERNATION_POSSIBLE
1746 bool
1747 depends on MMU
1748 default y if ARCH_SUSPEND_POSSIBLE
1749
1750 endmenu
1751
1752 source "arch/arm/Kconfig.assembler"
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