1 /*
2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun6i-rtc.h>
46 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
47 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49
50 / {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
54
55 chosen {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges;
59
60 framebuffer-lcd {
61 compatible = "allwinner,simple-framebuffer",
62 "simple-framebuffer";
63 allwinner,pipeline = "mixer0-lcd0";
64 clocks = <&display_clocks CLK_MIXER0>,
65 <&ccu CLK_TCON0>;
66 status = "disabled";
67 };
68 };
69
70 cpus {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 cpu@0 {
75 compatible = "arm,cortex-a7";
76 device_type = "cpu";
77 reg = <0>;
78 clocks = <&ccu CLK_CPU>;
79 };
80 };
81
82 de: display-engine {
83 compatible = "allwinner,sun8i-v3s-display-engine";
84 allwinner,pipelines = <&mixer0>;
85 status = "disabled";
86 };
87
88 timer {
89 compatible = "arm,armv7-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
94 };
95
96 clocks {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
100
101 osc24M: osc24M-clk {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 clock-frequency = <24000000>;
105 clock-accuracy = <50000>;
106 clock-output-names = "osc24M";
107 };
108
109 osc32k: osc32k-clk {
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 clock-frequency = <32768>;
113 clock-accuracy = <50000>;
114 clock-output-names = "ext-osc32k";
115 };
116 };
117
118 soc {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges;
123
124 display_clocks: clock@1000000 {
125 compatible = "allwinner,sun8i-v3s-de2-clk";
126 reg = <0x01000000 0x10000>;
127 clocks = <&ccu CLK_BUS_DE>,
128 <&ccu CLK_DE>;
129 clock-names = "bus",
130 "mod";
131 resets = <&ccu RST_BUS_DE>;
132 #clock-cells = <1>;
133 #reset-cells = <1>;
134 };
135
136 mixer0: mixer@1100000 {
137 compatible = "allwinner,sun8i-v3s-de2-mixer";
138 reg = <0x01100000 0x100000>;
139 clocks = <&display_clocks 0>,
140 <&display_clocks 6>;
141 clock-names = "bus",
142 "mod";
143 resets = <&display_clocks 0>;
144
145 ports {
146 #address-cells = <1>;
147 #size-cells = <0>;
148
149 mixer0_out: port@1 {
150 reg = <1>;
151
152 mixer0_out_tcon0: endpoint {
153 remote-endpoint = <&tcon0_in_mixer0>;
154 };
155 };
156 };
157 };
158
159 syscon: system-control@1c00000 {
160 compatible = "allwinner,sun8i-v3s-system-control",
161 "allwinner,sun8i-h3-system-control";
162 reg = <0x01c00000 0xd0>;
163 #address-cells = <1>;
164 #size-cells = <1>;
165 ranges;
166 };
167
168 nmi_intc: interrupt-controller@1c000d0 {
169 compatible = "allwinner,sun8i-v3s-nmi",
170 "allwinner,sun9i-a80-nmi";
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 reg = <0x01c000d0 0x0c>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175 };
176
177 dma: dma-controller@1c02000 {
178 compatible = "allwinner,sun8i-v3s-dma";
179 reg = <0x01c02000 0x1000>;
180 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&ccu CLK_BUS_DMA>;
182 resets = <&ccu RST_BUS_DMA>;
183 #dma-cells = <1>;
184 };
185
186 tcon0: lcd-controller@1c0c000 {
187 compatible = "allwinner,sun8i-v3s-tcon";
188 reg = <0x01c0c000 0x1000>;
189 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&ccu CLK_BUS_TCON0>,
191 <&ccu CLK_TCON0>;
192 clock-names = "ahb",
193 "tcon-ch0";
194 clock-output-names = "tcon-data-clock";
195 #clock-cells = <0>;
196 resets = <&ccu RST_BUS_TCON0>;
197 reset-names = "lcd";
198 status = "disabled";
199
200 ports {
201 #address-cells = <1>;
202 #size-cells = <0>;
203
204 tcon0_in: port@0 {
205 reg = <0>;
206
207 tcon0_in_mixer0: endpoint {
208 remote-endpoint = <&mixer0_out_tcon0>;
209 };
210 };
211
212 tcon0_out: port@1 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 reg = <1>;
216 };
217 };
218 };
219
220
221 mmc0: mmc@1c0f000 {
222 compatible = "allwinner,sun7i-a20-mmc";
223 reg = <0x01c0f000 0x1000>;
224 clocks = <&ccu CLK_BUS_MMC0>,
225 <&ccu CLK_MMC0>,
226 <&ccu CLK_MMC0_OUTPUT>,
227 <&ccu CLK_MMC0_SAMPLE>;
228 clock-names = "ahb",
229 "mmc",
230 "output",
231 "sample";
232 resets = <&ccu RST_BUS_MMC0>;
233 reset-names = "ahb";
234 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&mmc0_pins>;
237 status = "disabled";
238 #address-cells = <1>;
239 #size-cells = <0>;
240 };
241
242 mmc1: mmc@1c10000 {
243 compatible = "allwinner,sun7i-a20-mmc";
244 reg = <0x01c10000 0x1000>;
245 clocks = <&ccu CLK_BUS_MMC1>,
246 <&ccu CLK_MMC1>,
247 <&ccu CLK_MMC1_OUTPUT>,
248 <&ccu CLK_MMC1_SAMPLE>;
249 clock-names = "ahb",
250 "mmc",
251 "output",
252 "sample";
253 resets = <&ccu RST_BUS_MMC1>;
254 reset-names = "ahb";
255 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&mmc1_pins>;
258 status = "disabled";
259 #address-cells = <1>;
260 #size-cells = <0>;
261 };
262
263 mmc2: mmc@1c11000 {
264 compatible = "allwinner,sun7i-a20-mmc";
265 reg = <0x01c11000 0x1000>;
266 clocks = <&ccu CLK_BUS_MMC2>,
267 <&ccu CLK_MMC2>,
268 <&ccu CLK_MMC2_OUTPUT>,
269 <&ccu CLK_MMC2_SAMPLE>;
270 clock-names = "ahb",
271 "mmc",
272 "output",
273 "sample";
274 resets = <&ccu RST_BUS_MMC2>;
275 reset-names = "ahb";
276 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
277 status = "disabled";
278 #address-cells = <1>;
279 #size-cells = <0>;
280 };
281
282 crypto@1c15000 {
283 compatible = "allwinner,sun8i-v3s-crypto",
284 "allwinner,sun8i-a33-crypto";
285 reg = <0x01c15000 0x1000>;
286 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
288 clock-names = "ahb", "mod";
289 dmas = <&dma 16>, <&dma 16>;
290 dma-names = "rx", "tx";
291 resets = <&ccu RST_BUS_CE>;
292 reset-names = "ahb";
293 };
294
295 usb_otg: usb@1c19000 {
296 compatible = "allwinner,sun8i-h3-musb";
297 reg = <0x01c19000 0x0400>;
298 clocks = <&ccu CLK_BUS_OTG>;
299 resets = <&ccu RST_BUS_OTG>;
300 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
301 interrupt-names = "mc";
302 phys = <&usbphy 0>;
303 phy-names = "usb";
304 extcon = <&usbphy 0>;
305 status = "disabled";
306 };
307
308 usbphy: phy@1c19400 {
309 compatible = "allwinner,sun8i-v3s-usb-phy";
310 reg = <0x01c19400 0x2c>,
311 <0x01c1a800 0x4>;
312 reg-names = "phy_ctrl",
313 "pmu0";
314 clocks = <&ccu CLK_USB_PHY0>;
315 clock-names = "usb0_phy";
316 resets = <&ccu RST_USB_PHY0>;
317 reset-names = "usb0_reset";
318 status = "disabled";
319 #phy-cells = <1>;
320 };
321
322 ehci: usb@1c1a000 {
323 compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
324 reg = <0x01c1a000 0x100>;
325 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
327 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
328 phys = <&usbphy 0>;
329 phy-names = "usb";
330 status = "disabled";
331 };
332
333 ohci: usb@1c1a400 {
334 compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
335 reg = <0x01c1a400 0x100>;
336 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
338 <&ccu CLK_USB_OHCI0>;
339 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
340 phys = <&usbphy 0>;
341 phy-names = "usb";
342 status = "disabled";
343 };
344
345 ccu: clock@1c20000 {
346 compatible = "allwinner,sun8i-v3s-ccu";
347 reg = <0x01c20000 0x400>;
348 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
349 clock-names = "hosc", "losc";
350 #clock-cells = <1>;
351 #reset-cells = <1>;
352 };
353
354 rtc: rtc@1c20400 {
355 #clock-cells = <1>;
356 compatible = "allwinner,sun8i-v3-rtc";
357 reg = <0x01c20400 0x54>;
358 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&osc32k>;
361 clock-output-names = "osc32k", "osc32k-out";
362 };
363
364 pio: pinctrl@1c20800 {
365 compatible = "allwinner,sun8i-v3s-pinctrl";
366 reg = <0x01c20800 0x400>;
367 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
370 <&rtc CLK_OSC32K>;
371 clock-names = "apb", "hosc", "losc";
372 gpio-controller;
373 #gpio-cells = <3>;
374 interrupt-controller;
375 #interrupt-cells = <3>;
376
377 /omit-if-no-ref/
378 csi0_mclk_pin: csi0-mclk-pin {
379 pins = "PE20";
380 function = "csi_mipi";
381 };
382
383 /omit-if-no-ref/
384 csi1_8bit_pins: csi1-8bit-pins {
385 pins = "PE0", "PE2", "PE3", "PE8", "PE9",
386 "PE10", "PE11", "PE12", "PE13", "PE14",
387 "PE15";
388 function = "csi";
389 };
390
391 /omit-if-no-ref/
392 csi1_mclk_pin: csi1-mclk-pin {
393 pins = "PE1";
394 function = "csi";
395 };
396
397 i2c0_pins: i2c0-pins {
398 pins = "PB6", "PB7";
399 function = "i2c0";
400 };
401
402 /omit-if-no-ref/
403 i2c1_pb_pins: i2c1-pb-pins {
404 pins = "PB8", "PB9";
405 function = "i2c1";
406 };
407
408 /omit-if-no-ref/
409 i2c1_pe_pins: i2c1-pe-pins {
410 pins = "PE21", "PE22";
411 function = "i2c1";
412 };
413
414 uart0_pb_pins: uart0-pb-pins {
415 pins = "PB8", "PB9";
416 function = "uart0";
417 };
418
419 uart2_pins: uart2-pins {
420 pins = "PB0", "PB1";
421 function = "uart2";
422 };
423
424 mmc0_pins: mmc0-pins {
425 pins = "PF0", "PF1", "PF2", "PF3",
426 "PF4", "PF5";
427 function = "mmc0";
428 drive-strength = <30>;
429 bias-pull-up;
430 };
431
432 mmc1_pins: mmc1-pins {
433 pins = "PG0", "PG1", "PG2", "PG3",
434 "PG4", "PG5";
435 function = "mmc1";
436 drive-strength = <30>;
437 bias-pull-up;
438 };
439
440 /omit-if-no-ref/
441 pwm0_pin: pwm0-pin {
442 pins = "PB4";
443 function = "pwm0";
444 };
445
446 /omit-if-no-ref/
447 pwm1_pin: pwm1-pin {
448 pins = "PB5";
449 function = "pwm1";
450 };
451
452 spi0_pins: spi0-pins {
453 pins = "PC0", "PC1", "PC2", "PC3";
454 function = "spi0";
455 };
456 };
457
458 timer@1c20c00 {
459 compatible = "allwinner,sun8i-v3s-timer";
460 reg = <0x01c20c00 0xa0>;
461 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&osc24M>;
465 };
466
467 wdt0: watchdog@1c20ca0 {
468 compatible = "allwinner,sun6i-a31-wdt";
469 reg = <0x01c20ca0 0x20>;
470 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&osc24M>;
472 };
473
474 pwm: pwm@1c21400 {
475 compatible = "allwinner,sun8i-v3s-pwm",
476 "allwinner,sun7i-a20-pwm";
477 reg = <0x01c21400 0xc>;
478 clocks = <&osc24M>;
479 #pwm-cells = <3>;
480 status = "disabled";
481 };
482
483 lradc: lradc@1c22800 {
484 compatible = "allwinner,sun4i-a10-lradc-keys";
485 reg = <0x01c22800 0x400>;
486 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
487 status = "disabled";
488 };
489
490 codec: codec@1c22c00 {
491 #sound-dai-cells = <0>;
492 compatible = "allwinner,sun8i-v3s-codec";
493 reg = <0x01c22c00 0x400>;
494 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
496 clock-names = "apb", "codec";
497 resets = <&ccu RST_BUS_CODEC>;
498 dmas = <&dma 15>, <&dma 15>;
499 dma-names = "rx", "tx";
500 allwinner,codec-analog-controls = <&codec_analog>;
501 status = "disabled";
502 };
503
504 codec_analog: codec-analog@1c23000 {
505 compatible = "allwinner,sun8i-v3s-codec-analog";
506 reg = <0x01c23000 0x4>;
507 };
508
509 uart0: serial@1c28000 {
510 compatible = "snps,dw-apb-uart";
511 reg = <0x01c28000 0x400>;
512 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
513 reg-shift = <2>;
514 reg-io-width = <4>;
515 clocks = <&ccu CLK_BUS_UART0>;
516 dmas = <&dma 6>, <&dma 6>;
517 dma-names = "tx", "rx";
518 resets = <&ccu RST_BUS_UART0>;
519 status = "disabled";
520 };
521
522 uart1: serial@1c28400 {
523 compatible = "snps,dw-apb-uart";
524 reg = <0x01c28400 0x400>;
525 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
526 reg-shift = <2>;
527 reg-io-width = <4>;
528 clocks = <&ccu CLK_BUS_UART1>;
529 dmas = <&dma 7>, <&dma 7>;
530 dma-names = "tx", "rx";
531 resets = <&ccu RST_BUS_UART1>;
532 status = "disabled";
533 };
534
535 uart2: serial@1c28800 {
536 compatible = "snps,dw-apb-uart";
537 reg = <0x01c28800 0x400>;
538 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
539 reg-shift = <2>;
540 reg-io-width = <4>;
541 clocks = <&ccu CLK_BUS_UART2>;
542 dmas = <&dma 8>, <&dma 8>;
543 dma-names = "tx", "rx";
544 resets = <&ccu RST_BUS_UART2>;
545 pinctrl-0 = <&uart2_pins>;
546 pinctrl-names = "default";
547 status = "disabled";
548 };
549
550 i2c0: i2c@1c2ac00 {
551 compatible = "allwinner,sun6i-a31-i2c";
552 reg = <0x01c2ac00 0x400>;
553 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&ccu CLK_BUS_I2C0>;
555 resets = <&ccu RST_BUS_I2C0>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c0_pins>;
558 status = "disabled";
559 #address-cells = <1>;
560 #size-cells = <0>;
561 };
562
563 i2c1: i2c@1c2b000 {
564 compatible = "allwinner,sun6i-a31-i2c";
565 reg = <0x01c2b000 0x400>;
566 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&ccu CLK_BUS_I2C1>;
568 resets = <&ccu RST_BUS_I2C1>;
569 status = "disabled";
570 #address-cells = <1>;
571 #size-cells = <0>;
572 };
573
574 emac: ethernet@1c30000 {
575 compatible = "allwinner,sun8i-v3s-emac";
576 syscon = <&syscon>;
577 reg = <0x01c30000 0x10000>;
578 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
579 interrupt-names = "macirq";
580 resets = <&ccu RST_BUS_EMAC>;
581 reset-names = "stmmaceth";
582 clocks = <&ccu CLK_BUS_EMAC>;
583 clock-names = "stmmaceth";
584 phy-handle = <&int_mii_phy>;
585 phy-mode = "mii";
586 status = "disabled";
587
588 mdio: mdio {
589 #address-cells = <1>;
590 #size-cells = <0>;
591 compatible = "snps,dwmac-mdio";
592 };
593
594 mdio_mux: mdio-mux {
595 compatible = "allwinner,sun8i-h3-mdio-mux";
596 #address-cells = <1>;
597 #size-cells = <0>;
598
599 mdio-parent-bus = <&mdio>;
600 /* Only one MDIO is usable at the time */
601 internal_mdio: mdio@1 {
602 compatible = "allwinner,sun8i-h3-mdio-internal";
603 reg = <1>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606
607 int_mii_phy: ethernet-phy@1 {
608 compatible = "ethernet-phy-ieee802.3-c22";
609 reg = <1>;
610 clocks = <&ccu CLK_BUS_EPHY>;
611 resets = <&ccu RST_BUS_EPHY>;
612 };
613 };
614 };
615 };
616
617 spi0: spi@1c68000 {
618 compatible = "allwinner,sun8i-h3-spi";
619 reg = <0x01c68000 0x1000>;
620 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
622 clock-names = "ahb", "mod";
623 dmas = <&dma 23>, <&dma 23>;
624 dma-names = "rx", "tx";
625 pinctrl-names = "default";
626 pinctrl-0 = <&spi0_pins>;
627 resets = <&ccu RST_BUS_SPI0>;
628 status = "disabled";
629 #address-cells = <1>;
630 #size-cells = <0>;
631 };
632
633 gic: interrupt-controller@1c81000 {
634 compatible = "arm,gic-400";
635 reg = <0x01c81000 0x1000>,
636 <0x01c82000 0x2000>,
637 <0x01c84000 0x2000>,
638 <0x01c86000 0x2000>;
639 interrupt-controller;
640 #interrupt-cells = <3>;
641 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
642 };
643
644 csi1: camera@1cb4000 {
645 compatible = "allwinner,sun8i-v3s-csi";
646 reg = <0x01cb4000 0x3000>;
647 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&ccu CLK_BUS_CSI>,
649 <&ccu CLK_CSI1_SCLK>,
650 <&ccu CLK_DRAM_CSI>;
651 clock-names = "bus", "mod", "ram";
652 resets = <&ccu RST_BUS_CSI>;
653 status = "disabled";
654 };
655 };
656 };
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