1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // Copyright 2019 IBM Corp.
3
4 /dts-v1/;
5
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
8
9 / {
10 model = "AST2600 EVB";
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
12
13 aliases {
14 serial4 = &uart5;
15 };
16
17 chosen {
18 bootargs = "console=ttyS4,115200n8";
19 };
20
21 memory@80000000 {
22 device_type = "memory";
23 reg = <0x80000000 0x80000000>;
24 };
25
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 ranges;
30
31 video_engine_memory: video {
32 size = <0x04000000>;
33 alignment = <0x01000000>;
34 compatible = "shared-dma-pool";
35 reusable;
36 };
37
38 gfx_memory: framebuffer {
39 size = <0x01000000>;
40 alignment = <0x01000000>;
41 compatible = "shared-dma-pool";
42 reusable;
43 };
44 };
45
46 vcc_sdhci0: regulator-vcc-sdhci0 {
47 compatible = "regulator-fixed";
48 regulator-name = "SDHCI0 Vcc";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 };
54
55 vccq_sdhci0: regulator-vccq-sdhci0 {
56 compatible = "regulator-gpio";
57 regulator-name = "SDHCI0 VccQ";
58 regulator-min-microvolt = <1800000>;
59 regulator-max-microvolt = <3300000>;
60 gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
61 gpios-states = <1>;
62 states = <3300000 1>,
63 <1800000 0>;
64 };
65
66 vcc_sdhci1: regulator-vcc-sdhci1 {
67 compatible = "regulator-fixed";
68 regulator-name = "SDHCI1 Vcc";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
72 enable-active-high;
73 };
74
75 vccq_sdhci1: regulator-vccq-sdhci1 {
76 compatible = "regulator-gpio";
77 regulator-name = "SDHCI1 VccQ";
78 regulator-min-microvolt = <1800000>;
79 regulator-max-microvolt = <3300000>;
80 gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
81 gpios-states = <1>;
82 states = <3300000 1>,
83 <1800000 0>;
84 };
85 };
86
87 &mdio0 {
88 status = "okay";
89
90 ethphy0: ethernet-phy@0 {
91 compatible = "ethernet-phy-ieee802.3-c22";
92 reg = <0>;
93 };
94 };
95
96 &mdio1 {
97 status = "okay";
98
99 ethphy1: ethernet-phy@0 {
100 compatible = "ethernet-phy-ieee802.3-c22";
101 reg = <0>;
102 };
103 };
104
105 &mdio2 {
106 status = "okay";
107
108 ethphy2: ethernet-phy@0 {
109 compatible = "ethernet-phy-ieee802.3-c22";
110 reg = <0>;
111 };
112 };
113
114 &mdio3 {
115 status = "okay";
116
117 ethphy3: ethernet-phy@0 {
118 compatible = "ethernet-phy-ieee802.3-c22";
119 reg = <0>;
120 };
121 };
122
123 &mac0 {
124 status = "okay";
125
126 phy-mode = "rgmii-rxid";
127 phy-handle = <ðphy0>;
128
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_rgmii1_default>;
131 };
132
133
134 &mac1 {
135 status = "okay";
136
137 phy-mode = "rgmii-rxid";
138 phy-handle = <ðphy1>;
139
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_rgmii2_default>;
142 };
143
144 &mac2 {
145 status = "okay";
146
147 phy-mode = "rgmii";
148 phy-handle = <ðphy2>;
149
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_rgmii3_default>;
152 };
153
154 &mac3 {
155 status = "okay";
156
157 phy-mode = "rgmii";
158 phy-handle = <ðphy3>;
159
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_rgmii4_default>;
162 };
163
164 &emmc_controller {
165 status = "okay";
166 };
167
168 &emmc {
169 non-removable;
170 bus-width = <4>;
171 max-frequency = <100000000>;
172 clk-phase-mmc-hs200 = <9>, <225>;
173 };
174
175 &rtc {
176 status = "okay";
177 };
178
179 &fmc {
180 status = "okay";
181 flash@0 {
182 status = "okay";
183 m25p,fast-read;
184 label = "bmc";
185 spi-rx-bus-width = <4>;
186 spi-max-frequency = <50000000>;
187 #include "openbmc-flash-layout-64.dtsi"
188 };
189 };
190
191 &spi1 {
192 status = "okay";
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_spi1_default>;
195
196 flash@0 {
197 status = "okay";
198 m25p,fast-read;
199 label = "pnor";
200 spi-rx-bus-width = <4>;
201 spi-max-frequency = <100000000>;
202 };
203 };
204
205 &uart5 {
206 // Workaround for A0
207 compatible = "snps,dw-apb-uart";
208 };
209
210 &i2c0 {
211 status = "okay";
212 };
213
214 &i2c1 {
215 status = "okay";
216 };
217
218 &i2c2 {
219 status = "okay";
220 };
221
222 &i2c3 {
223 status = "okay";
224 };
225
226 &i2c4 {
227 status = "okay";
228 };
229
230 &i2c5 {
231 status = "okay";
232 };
233
234 &i2c6 {
235 status = "okay";
236 };
237
238 &i2c7 {
239 status = "okay";
240
241 temp@2e {
242 compatible = "adi,adt7490";
243 reg = <0x2e>;
244 };
245
246 eeprom@50 {
247 compatible = "atmel,24c08";
248 reg = <0x50>;
249 pagesize = <16>;
250 };
251 };
252
253 &i2c8 {
254 status = "okay";
255
256 lm75@4d {
257 compatible = "national,lm75";
258 reg = <0x4d>;
259 };
260 };
261
262 &i2c9 {
263 status = "okay";
264 };
265
266 &i2c12 {
267 status = "okay";
268 };
269
270 &i2c13 {
271 status = "okay";
272 };
273
274 &i2c14 {
275 status = "okay";
276 };
277
278 &i2c15 {
279 status = "okay";
280 };
281
282 &fsim0 {
283 status = "okay";
284 };
285
286 &ehci1 {
287 status = "okay";
288 };
289
290 &uhci {
291 status = "okay";
292 };
293
294 &sdc {
295 status = "okay";
296 };
297
298 /*
299 * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be
300 * toggled by GPIO pins.
301 * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the
302 * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to
303 * a 1.8v and a 3.3v power load switch that provides signal voltage to
304 * sdhci0 bus.
305 * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled.
306 * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal
307 * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled,
308 * sdhci0 signal voltage becomes 1.8v.
309 * AST2600-A2 EVB also supports toggling signal voltage for sdhci1.
310 * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3
311 * as power-switch-gpio.
312 */
313 &sdhci0 {
314 status = "okay";
315 bus-width = <4>;
316 max-frequency = <100000000>;
317 sdhci-drive-type = /bits/ 8 <3>;
318 sdhci-caps-mask = <0x7 0x0>;
319 sdhci,wp-inverted;
320 vmmc-supply = <&vcc_sdhci0>;
321 vqmmc-supply = <&vccq_sdhci0>;
322 clk-phase-sd-hs = <7>, <200>;
323 };
324
325 &sdhci1 {
326 status = "okay";
327 bus-width = <4>;
328 max-frequency = <100000000>;
329 sdhci-drive-type = /bits/ 8 <3>;
330 sdhci-caps-mask = <0x7 0x0>;
331 sdhci,wp-inverted;
332 vmmc-supply = <&vcc_sdhci1>;
333 vqmmc-supply = <&vccq_sdhci1>;
334 clk-phase-sd-hs = <7>, <200>;
335 };
336
337 &vhub {
338 status = "okay";
339 pinctrl-names = "default";
340 };
341
342 &video {
343 status = "okay";
344 memory-region = <&video_engine_memory>;
345 };
346
347 &gfx {
348 status = "okay";
349 memory-region = <&gfx_memory>;
350 };
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