1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
5
6 / {
7 model = "Ampere Mt. Jade BMC";
8 compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
9
10 aliases {
11 /*
12 * i2c bus 50-57 assigned to NVMe slot 0-7
13 */
14 i2c50 = &nvmeslot_0;
15 i2c51 = &nvmeslot_1;
16 i2c52 = &nvmeslot_2;
17 i2c53 = &nvmeslot_3;
18 i2c54 = &nvmeslot_4;
19 i2c55 = &nvmeslot_5;
20 i2c56 = &nvmeslot_6;
21 i2c57 = &nvmeslot_7;
22
23 /*
24 * i2c bus 60-67 assigned to NVMe slot 8-15
25 */
26 i2c60 = &nvmeslot_8;
27 i2c61 = &nvmeslot_9;
28 i2c62 = &nvmeslot_10;
29 i2c63 = &nvmeslot_11;
30 i2c64 = &nvmeslot_12;
31 i2c65 = &nvmeslot_13;
32 i2c66 = &nvmeslot_14;
33 i2c67 = &nvmeslot_15;
34
35 /*
36 * i2c bus 70-77 assigned to NVMe slot 16-23
37 */
38 i2c70 = &nvmeslot_16;
39 i2c71 = &nvmeslot_17;
40 i2c72 = &nvmeslot_18;
41 i2c73 = &nvmeslot_19;
42 i2c74 = &nvmeslot_20;
43 i2c75 = &nvmeslot_21;
44 i2c76 = &nvmeslot_22;
45 i2c77 = &nvmeslot_23;
46
47 /*
48 * i2c bus 80-81 assigned to NVMe M2 slot 0-1
49 */
50 i2c80 = &nvme_m2_0;
51 i2c81 = &nvme_m2_1;
52 };
53
54 chosen {
55 stdout-path = &uart5;
56 bootargs = "console=ttyS4,115200 earlycon";
57 };
58
59 memory@80000000 {
60 reg = <0x80000000 0x20000000>;
61 };
62
63 reserved-memory {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
67
68 vga_memory: framebuffer@9f000000 {
69 no-map;
70 reg = <0x9f000000 0x01000000>; /* 16M */
71 };
72
73 gfx_memory: framebuffer {
74 size = <0x01000000>;
75 alignment = <0x01000000>;
76 compatible = "shared-dma-pool";
77 reusable;
78 };
79
80 video_engine_memory: jpegbuffer {
81 size = <0x02000000>; /* 32M */
82 alignment = <0x01000000>;
83 compatible = "shared-dma-pool";
84 reusable;
85 };
86 };
87
88 leds {
89 compatible = "gpio-leds";
90
91 fault {
92 gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>;
93 };
94
95 identify {
96 gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
97 };
98 };
99
100 gpioA0mux: mux-controller {
101 compatible = "gpio-mux";
102 #mux-control-cells = <0>;
103 mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>;
104 };
105
106 adc0mux: adc0mux {
107 compatible = "io-channel-mux";
108 io-channels = <&adc 0>;
109 #io-channel-cells = <1>;
110 io-channel-names = "parent";
111 mux-controls = <&gpioA0mux>;
112 channels = "s0", "s1";
113 };
114
115 adc1mux: adc1mux {
116 compatible = "io-channel-mux";
117 io-channels = <&adc 1>;
118 #io-channel-cells = <1>;
119 io-channel-names = "parent";
120 mux-controls = <&gpioA0mux>;
121 channels = "s0", "s1";
122 };
123
124 adc2mux: adc2mux {
125 compatible = "io-channel-mux";
126 io-channels = <&adc 2>;
127 #io-channel-cells = <1>;
128 io-channel-names = "parent";
129 mux-controls = <&gpioA0mux>;
130 channels = "s0", "s1";
131 };
132
133 adc3mux: adc3mux {
134 compatible = "io-channel-mux";
135 io-channels = <&adc 3>;
136 #io-channel-cells = <1>;
137 io-channel-names = "parent";
138 mux-controls = <&gpioA0mux>;
139 channels = "s0", "s1";
140 };
141
142 adc4mux: adc4mux {
143 compatible = "io-channel-mux";
144 io-channels = <&adc 4>;
145 #io-channel-cells = <1>;
146 io-channel-names = "parent";
147 mux-controls = <&gpioA0mux>;
148 channels = "s0", "s1";
149 };
150
151 adc5mux: adc5mux {
152 compatible = "io-channel-mux";
153 io-channels = <&adc 5>;
154 #io-channel-cells = <1>;
155 io-channel-names = "parent";
156 mux-controls = <&gpioA0mux>;
157 channels = "s0", "s1";
158 };
159
160 adc6mux: adc6mux {
161 compatible = "io-channel-mux";
162 io-channels = <&adc 6>;
163 #io-channel-cells = <1>;
164 io-channel-names = "parent";
165 mux-controls = <&gpioA0mux>;
166 channels = "s0", "s1";
167 };
168
169 adc7mux: adc7mux {
170 compatible = "io-channel-mux";
171 io-channels = <&adc 7>;
172 #io-channel-cells = <1>;
173 io-channel-names = "parent";
174 mux-controls = <&gpioA0mux>;
175 channels = "s0", "s1";
176 };
177
178 adc8mux: adc8mux {
179 compatible = "io-channel-mux";
180 io-channels = <&adc 8>;
181 #io-channel-cells = <1>;
182 io-channel-names = "parent";
183 mux-controls = <&gpioA0mux>;
184 channels = "s0", "s1";
185 };
186
187 adc9mux: adc9mux {
188 compatible = "io-channel-mux";
189 io-channels = <&adc 9>;
190 #io-channel-cells = <1>;
191 io-channel-names = "parent";
192 mux-controls = <&gpioA0mux>;
193 channels = "s0", "s1";
194 };
195
196 adc10mux: adc10mux {
197 compatible = "io-channel-mux";
198 io-channels = <&adc 10>;
199 #io-channel-cells = <1>;
200 io-channel-names = "parent";
201 mux-controls = <&gpioA0mux>;
202 channels = "s0", "s1";
203 };
204
205 adc11mux: adc11mux {
206 compatible = "io-channel-mux";
207 io-channels = <&adc 11>;
208 #io-channel-cells = <1>;
209 io-channel-names = "parent";
210 mux-controls = <&gpioA0mux>;
211 channels = "s0", "s1";
212 };
213
214 adc12mux: adc12mux {
215 compatible = "io-channel-mux";
216 io-channels = <&adc 12>;
217 #io-channel-cells = <1>;
218 io-channel-names = "parent";
219 mux-controls = <&gpioA0mux>;
220 channels = "s0", "s1";
221 };
222
223 adc13mux: adc13mux {
224 compatible = "io-channel-mux";
225 io-channels = <&adc 13>;
226 #io-channel-cells = <1>;
227 io-channel-names = "parent";
228 mux-controls = <&gpioA0mux>;
229 channels = "s0", "s1";
230 };
231
232 iio-hwmon {
233 compatible = "iio-hwmon";
234 io-channels = <&adc0mux 0>, <&adc0mux 1>,
235 <&adc1mux 0>, <&adc1mux 1>,
236 <&adc2mux 0>, <&adc2mux 1>,
237 <&adc3mux 0>, <&adc3mux 1>,
238 <&adc4mux 0>, <&adc4mux 1>,
239 <&adc5mux 0>, <&adc5mux 1>,
240 <&adc6mux 0>, <&adc6mux 1>,
241 <&adc7mux 0>, <&adc7mux 1>,
242 <&adc8mux 0>, <&adc8mux 1>,
243 <&adc9mux 0>, <&adc9mux 1>,
244 <&adc10mux 0>, <&adc10mux 1>,
245 <&adc11mux 0>, <&adc11mux 1>,
246 <&adc12mux 0>, <&adc12mux 1>,
247 <&adc13mux 0>, <&adc13mux 1>,
248 <&adc 14>, <&adc 15>;
249 };
250 };
251
252 &fmc {
253 status = "okay";
254 flash@0 {
255 status = "okay";
256 m25p,fast-read;
257 label = "bmc";
258 /* spi-max-frequency = <50000000>; */
259 #include "openbmc-flash-layout-64.dtsi"
260 };
261
262 flash@1 {
263 status = "okay";
264 m25p,fast-read;
265 label = "alt-bmc";
266 #include "openbmc-flash-layout-64-alt.dtsi"
267 };
268 };
269
270 &spi1 {
271 status = "okay";
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_spi1_default>;
274
275 flash@0 {
276 status = "okay";
277 m25p,fast-read;
278 label = "pnor";
279 /* spi-max-frequency = <100000000>; */
280 partitions {
281 compatible = "fixed-partitions";
282 #address-cells = <1>;
283 #size-cells = <1>;
284 uefi@400000 {
285 reg = <0x400000 0x1C00000>;
286 label = "pnor-uefi";
287 };
288 };
289 };
290 };
291
292 &uart1 {
293 status = "okay";
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_txd1_default
296 &pinctrl_rxd1_default
297 &pinctrl_ncts1_default
298 &pinctrl_nrts1_default>;
299 };
300
301 &uart2 {
302 status = "okay";
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_txd2_default
305 &pinctrl_rxd2_default>;
306 };
307
308 &uart3 {
309 status = "okay";
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_txd3_default
312 &pinctrl_rxd3_default>;
313 };
314
315 &uart4 {
316 status = "okay";
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_txd4_default
319 &pinctrl_rxd4_default>;
320 };
321
322 /* The BMC's uart */
323 &uart5 {
324 status = "okay";
325 };
326
327 &mac0 {
328 status = "okay";
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_rmii1_default>;
331 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
332 <&syscon ASPEED_CLK_MAC1RCLK>;
333 clock-names = "MACCLK", "RCLK";
334 use-ncsi;
335 };
336
337 &mac1 {
338 status = "okay";
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
341 };
342
343 &i2c0 {
344 status = "okay";
345 ssif-bmc@10 {
346 compatible = "ssif-bmc";
347 reg = <0x10>;
348 };
349 };
350
351 &i2c1 {
352 status = "okay";
353 };
354
355 &i2c2 {
356 status = "okay";
357 smpro@4f {
358 compatible = "ampere,smpro";
359 reg = <0x4f>;
360 };
361 smpro@4e {
362 compatible = "ampere,smpro";
363 reg = <0x4e>;
364 };
365 };
366
367 &i2c3 {
368 status = "okay";
369 eeprom@50 {
370 compatible = "microchip,24c64", "atmel,24c64";
371 reg = <0x50>;
372 pagesize = <32>;
373 };
374
375 inlet_mem2: tmp175@28 {
376 compatible = "ti,tmp175";
377 reg = <0x28>;
378 };
379
380 inlet_cpu: tmp175@29 {
381 compatible = "ti,tmp175";
382 reg = <0x29>;
383 };
384
385 inlet_mem1: tmp175@2a {
386 compatible = "ti,tmp175";
387 reg = <0x2a>;
388 };
389
390 outlet_cpu: tmp175@2b {
391 compatible = "ti,tmp175";
392 reg = <0x2b>;
393 };
394
395 outlet1: tmp175@2c {
396 compatible = "ti,tmp175";
397 reg = <0x2c>;
398 };
399
400 outlet2: tmp175@2d {
401 compatible = "ti,tmp175";
402 reg = <0x2d>;
403 };
404 };
405
406 &i2c4 {
407 status = "okay";
408 rtc@51 {
409 compatible = "nxp,pcf85063a";
410 reg = <0x51>;
411 };
412 };
413
414 &i2c5 {
415 status = "okay";
416 i2c-mux@70 {
417 compatible = "nxp,pca9548";
418 #address-cells = <1>;
419 #size-cells = <0>;
420 reg = <0x70>;
421 i2c-mux-idle-disconnect;
422
423 nvmeslot_0_7: i2c@3 {
424 #address-cells = <1>;
425 #size-cells = <0>;
426 reg = <0x3>;
427 };
428 };
429
430 i2c-mux@71 {
431 compatible = "nxp,pca9548";
432 #address-cells = <1>;
433 #size-cells = <0>;
434 reg = <0x71>;
435 i2c-mux-idle-disconnect;
436
437 nvmeslot_8_15: i2c@4 {
438 #address-cells = <1>;
439 #size-cells = <0>;
440 reg = <0x4>;
441 };
442
443 nvmeslot_16_23: i2c@3 {
444 #address-cells = <1>;
445 #size-cells = <0>;
446 reg = <0x3>;
447 };
448
449 };
450
451 i2c-mux@72 {
452 compatible = "nxp,pca9545";
453 #address-cells = <1>;
454 #size-cells = <0>;
455 reg = <0x72>;
456 i2c-mux-idle-disconnect;
457
458 nvme_m2_0: i2c@0 {
459 #address-cells = <1>;
460 #size-cells = <0>;
461 reg = <0x0>;
462 };
463
464 nvme_m2_1: i2c@1 {
465 #address-cells = <1>;
466 #size-cells = <0>;
467 reg = <0x1>;
468 };
469 };
470 };
471
472 &nvmeslot_0_7 {
473 status = "okay";
474
475 i2c-mux@75 {
476 compatible = "nxp,pca9548";
477 #address-cells = <1>;
478 #size-cells = <0>;
479 reg = <0x75>;
480 i2c-mux-idle-disconnect;
481
482 nvmeslot_0: i2c@0 {
483 #address-cells = <1>;
484 #size-cells = <0>;
485 reg = <0x0>;
486 };
487 nvmeslot_1: i2c@1 {
488 #address-cells = <1>;
489 #size-cells = <0>;
490 reg = <0x1>;
491 };
492 nvmeslot_2: i2c@2 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 reg = <0x2>;
496 };
497 nvmeslot_3: i2c@3 {
498 #address-cells = <1>;
499 #size-cells = <0>;
500 reg = <0x3>;
501 };
502 nvmeslot_4: i2c@4 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 reg = <0x4>;
506 };
507 nvmeslot_5: i2c@5 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 reg = <0x5>;
511 };
512 nvmeslot_6: i2c@6 {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 reg = <0x6>;
516 };
517 nvmeslot_7: i2c@7 {
518 #address-cells = <1>;
519 #size-cells = <0>;
520 reg = <0x7>;
521 };
522
523 };
524 };
525
526 &nvmeslot_8_15 {
527 status = "okay";
528
529 i2c-mux@75 {
530 compatible = "nxp,pca9548";
531 #address-cells = <1>;
532 #size-cells = <0>;
533 reg = <0x75>;
534 i2c-mux-idle-disconnect;
535
536 nvmeslot_8: i2c@0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 reg = <0x0>;
540 };
541 nvmeslot_9: i2c@1 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 reg = <0x1>;
545 };
546 nvmeslot_10: i2c@2 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 reg = <0x2>;
550 };
551 nvmeslot_11: i2c@3 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 reg = <0x3>;
555 };
556 nvmeslot_12: i2c@4 {
557 #address-cells = <1>;
558 #size-cells = <0>;
559 reg = <0x4>;
560 };
561 nvmeslot_13: i2c@5 {
562 #address-cells = <1>;
563 #size-cells = <0>;
564 reg = <0x5>;
565 };
566 nvmeslot_14: i2c@6 {
567 #address-cells = <1>;
568 #size-cells = <0>;
569 reg = <0x6>;
570 };
571 nvmeslot_15: i2c@7 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 reg = <0x7>;
575 };
576 };
577 };
578
579 &nvmeslot_16_23 {
580 status = "okay";
581
582 i2c-mux@75 {
583 compatible = "nxp,pca9548";
584 #address-cells = <1>;
585 #size-cells = <0>;
586 reg = <0x75>;
587 i2c-mux-idle-disconnect;
588
589 nvmeslot_16: i2c@0 {
590 #address-cells = <1>;
591 #size-cells = <0>;
592 reg = <0x0>;
593 };
594 nvmeslot_17: i2c@1 {
595 #address-cells = <1>;
596 #size-cells = <0>;
597 reg = <0x1>;
598 };
599 nvmeslot_18: i2c@2 {
600 #address-cells = <1>;
601 #size-cells = <0>;
602 reg = <0x2>;
603 };
604 nvmeslot_19: i2c@3 {
605 #address-cells = <1>;
606 #size-cells = <0>;
607 reg = <0x3>;
608 };
609 nvmeslot_20: i2c@4 {
610 #address-cells = <1>;
611 #size-cells = <0>;
612 reg = <0x4>;
613 };
614 nvmeslot_21: i2c@5 {
615 #address-cells = <1>;
616 #size-cells = <0>;
617 reg = <0x5>;
618 };
619 nvmeslot_22: i2c@6 {
620 #address-cells = <1>;
621 #size-cells = <0>;
622 reg = <0x6>;
623 };
624 nvmeslot_23: i2c@7 {
625 #address-cells = <1>;
626 #size-cells = <0>;
627 reg = <0x7>;
628 };
629 };
630 };
631
632 &i2c6 {
633 status = "okay";
634 psu@58 {
635 compatible = "pmbus";
636 reg = <0x58>;
637 };
638
639 psu@59 {
640 compatible = "pmbus";
641 reg = <0x59>;
642 };
643 };
644
645 &i2c7 {
646 status = "okay";
647 };
648
649 &i2c8 {
650 status = "okay";
651 };
652
653 &i2c9 {
654 status = "okay";
655 };
656
657 &i2c10 {
658 status = "okay";
659 adm1278@10 {
660 compatible = "adi,adm1278";
661 reg = <0x10>;
662 };
663
664 adm1278@11 {
665 compatible = "adi,adm1278";
666 reg = <0x11>;
667 };
668 };
669
670 &gfx {
671 status = "okay";
672 memory-region = <&gfx_memory>;
673 };
674
675 &pinctrl {
676 aspeed,external-nodes = <&gfx &lhc>;
677 };
678
679 &pwm_tacho {
680 status = "okay";
681 pinctrl-names = "default";
682 pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default
683 &pinctrl_pwm4_default &pinctrl_pwm5_default
684 &pinctrl_pwm6_default &pinctrl_pwm7_default>;
685
686 fan@0 {
687 reg = <0x02>;
688 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
689 };
690
691 fan@1 {
692 reg = <0x02>;
693 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
694 };
695
696 fan@2 {
697 reg = <0x03>;
698 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
699 };
700
701 fan@3 {
702 reg = <0x03>;
703 aspeed,fan-tach-ch = /bits/ 8 <0x07>;
704 };
705
706 fan@4 {
707 reg = <0x04>;
708 aspeed,fan-tach-ch = /bits/ 8 <0x08>;
709 };
710
711 fan@5 {
712 reg = <0x04>;
713 aspeed,fan-tach-ch = /bits/ 8 <0x09>;
714 };
715
716 fan@6 {
717 reg = <0x05>;
718 aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
719 };
720
721 fan@7 {
722 reg = <0x05>;
723 aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
724 };
725
726 fan@8 {
727 reg = <0x06>;
728 aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
729 };
730
731 fan@9 {
732 reg = <0x06>;
733 aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
734 };
735
736 fan@10 {
737 reg = <0x07>;
738 aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
739 };
740
741 fan@11 {
742 reg = <0x07>;
743 aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
744 };
745
746 };
747
748 &vhub {
749 status = "okay";
750 };
751
752 &adc {
753 status = "okay";
754 };
755
756 &video {
757 status = "okay";
758 memory-region = <&video_engine_memory>;
759 };
760
761 &gpio {
762 gpio-line-names =
763 /*A0-A7*/ "","","","host0-special-boot","","","","",
764 /*B0-B7*/ "i2c-backup-sel","","","",
765 "power-button","presence-cpu0","","",
766 /*C0-C7*/ "","","","","","","","",
767 /*D0-D7*/ "","","","","","","","",
768 /*E0-E7*/ "","","","","","","","",
769 /*F0-F7*/ "ps0-pgood","ps1-pgood","power-chassis-control","s0-ddr-save",
770 "power-chassis-good", "s1-ddr-save","","",
771 /*G0-G7*/ "host0-ready","host0-shd-req-n","host0-shd-ack-n",
772 "s0-overtemp-n","","","","",
773 /*H0-H7*/ "uart1-mode1","uart2-mode1","uart3-mode1","uart4-mode1",
774 "ps0-vin-good","ps1-vin-good","","i2c6-reset-n",
775 /*I0-I7*/ "presence-ps0","presence-ps1","s1-special-boot","","","","","",
776 /*J0-J7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n",
777 "host0-reboot-ack-n","","","","",
778 /*K0-K7*/ "","","","","","","","",
779 /*L0-L7*/ "","","","host0-sysreset-n","s0-spi-auth-fail-n","","","",
780 /*M0-M7*/ "","","","","s0-i2c9-alert-n","s1-i2c9-alert-n","","",
781 /*N0-N7*/ "","","","","","","","",
782 /*O0-O7*/ "","","","","","","","",
783 /*P0-P7*/ "","","","","","","","",
784 /*Q0-Q7*/ "","","","","","identify-button","led-identify","",
785 /*R0-R7*/ "","","ext-hightemp-n","","ocp-main-pwren","reset-button","","",
786 /*S0-S7*/ "s0-vr-hot-n","s1-vr-hot-n","","",
787 "rtc-battery-voltage-read-enable","vr-pmbus-sel-n","","",
788 /*T0-T7*/ "","","","","","","","",
789 /*U0-U7*/ "","","","","","","","",
790 /*V0-V7*/ "","","","","","","","",
791 /*W0-W7*/ "","","","","","","","",
792 /*X0-X7*/ "","","","","","","","",
793 /*Y0-Y7*/ "","","","bmc-vga-en-n","","","","",
794 /*Z0-Z7*/ "s0-plimit","s1-fault-alert","s1-fw-boot-ok","s0-rtc-lock","",
795 "s1-sys-auth-failure-n","s1-overtemp-n","",
796 /*AA0-AA7*/ "","","","","","","","",
797 /*AB0-AB7*/ "s1-hightemp-n","s1-plimit","s0-ddr-addr","s1-ddr-addr","","",
798 "","",
799 /*AC0-AC7*/ "sys-pwr-gd","","spi0-program-sel","spi0-backup-sel","bmc-ok",
800 "","presence-cpu1","ocp-pgood";
801
802 i2c4-o-en-hog {
803 gpio-hog;
804 gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
805 output-high;
806 line-name = "i2c4-o-en";
807 };
808
809 ocp-aux-pwren-hog {
810 gpio-hog;
811 gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
812 output-high;
813 line-name = "ocp-aux-pwren";
814 };
815
816 bmc-ready {
817 gpio-hog;
818 gpios = <ASPEED_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
819 output-high;
820 line-name = "bmc-ready";
821 };
822 };
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