1 // SPDX-License-Identifier: GPL-2.0+ 2 /dts-v1/; 3 #include "aspeed-g5.dtsi" 4 #include <dt-bindings/gpio/aspeed-gpio.h> 5 6 / { 7 model = "Ampere Mt. Jade BMC"; 8 compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; 9 10 aliases { 11 /* 12 * i2c bus 50-57 assigned to NVMe slot 0-7 13 */ 14 i2c50 = &nvmeslot_0; 15 i2c51 = &nvmeslot_1; 16 i2c52 = &nvmeslot_2; 17 i2c53 = &nvmeslot_3; 18 i2c54 = &nvmeslot_4; 19 i2c55 = &nvmeslot_5; 20 i2c56 = &nvmeslot_6; 21 i2c57 = &nvmeslot_7; 22 23 /* 24 * i2c bus 60-67 assigned to NVMe slot 8-15 25 */ 26 i2c60 = &nvmeslot_8; 27 i2c61 = &nvmeslot_9; 28 i2c62 = &nvmeslot_10; 29 i2c63 = &nvmeslot_11; 30 i2c64 = &nvmeslot_12; 31 i2c65 = &nvmeslot_13; 32 i2c66 = &nvmeslot_14; 33 i2c67 = &nvmeslot_15; 34 35 /* 36 * i2c bus 70-77 assigned to NVMe slot 16-23 37 */ 38 i2c70 = &nvmeslot_16; 39 i2c71 = &nvmeslot_17; 40 i2c72 = &nvmeslot_18; 41 i2c73 = &nvmeslot_19; 42 i2c74 = &nvmeslot_20; 43 i2c75 = &nvmeslot_21; 44 i2c76 = &nvmeslot_22; 45 i2c77 = &nvmeslot_23; 46 47 /* 48 * i2c bus 80-81 assigned to NVMe M2 slot 0-1 49 */ 50 i2c80 = &nvme_m2_0; 51 i2c81 = &nvme_m2_1; 52 53 /* 54 * i2c bus 82 assigned to OCP slot 55 */ 56 i2c82 = &ocpslot; 57 }; 58 59 chosen { 60 stdout-path = &uart5; 61 bootargs = "console=ttyS4,115200 earlycon"; 62 }; 63 64 memory@80000000 { 65 reg = <0x80000000 0x20000000>; 66 }; 67 68 reserved-memory { 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges; 72 73 vga_memory: framebuffer@9f000000 { 74 no-map; 75 reg = <0x9f000000 0x01000000>; /* 16M */ 76 }; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_engine_memory: jpegbuffer { 86 size = <0x02000000>; /* 32M */ 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 reusable; 90 }; 91 }; 92 93 leds { 94 compatible = "gpio-leds"; 95 96 fault { 97 gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>; 98 }; 99 100 identify { 101 gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>; 102 }; 103 }; 104 105 gpioA0mux: mux-controller { 106 compatible = "gpio-mux"; 107 #mux-control-cells = <0>; 108 mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>; 109 }; 110 111 adc0mux: adc0mux { 112 compatible = "io-channel-mux"; 113 io-channels = <&adc 0>; 114 #io-channel-cells = <1>; 115 io-channel-names = "parent"; 116 mux-controls = <&gpioA0mux>; 117 channels = "s0", "s1"; 118 }; 119 120 adc1mux: adc1mux { 121 compatible = "io-channel-mux"; 122 io-channels = <&adc 1>; 123 #io-channel-cells = <1>; 124 io-channel-names = "parent"; 125 mux-controls = <&gpioA0mux>; 126 channels = "s0", "s1"; 127 }; 128 129 adc2mux: adc2mux { 130 compatible = "io-channel-mux"; 131 io-channels = <&adc 2>; 132 #io-channel-cells = <1>; 133 io-channel-names = "parent"; 134 mux-controls = <&gpioA0mux>; 135 channels = "s0", "s1"; 136 }; 137 138 adc3mux: adc3mux { 139 compatible = "io-channel-mux"; 140 io-channels = <&adc 3>; 141 #io-channel-cells = <1>; 142 io-channel-names = "parent"; 143 mux-controls = <&gpioA0mux>; 144 channels = "s0", "s1"; 145 }; 146 147 adc4mux: adc4mux { 148 compatible = "io-channel-mux"; 149 io-channels = <&adc 4>; 150 #io-channel-cells = <1>; 151 io-channel-names = "parent"; 152 mux-controls = <&gpioA0mux>; 153 channels = "s0", "s1"; 154 }; 155 156 adc5mux: adc5mux { 157 compatible = "io-channel-mux"; 158 io-channels = <&adc 5>; 159 #io-channel-cells = <1>; 160 io-channel-names = "parent"; 161 mux-controls = <&gpioA0mux>; 162 channels = "s0", "s1"; 163 }; 164 165 adc6mux: adc6mux { 166 compatible = "io-channel-mux"; 167 io-channels = <&adc 6>; 168 #io-channel-cells = <1>; 169 io-channel-names = "parent"; 170 mux-controls = <&gpioA0mux>; 171 channels = "s0", "s1"; 172 }; 173 174 adc7mux: adc7mux { 175 compatible = "io-channel-mux"; 176 io-channels = <&adc 7>; 177 #io-channel-cells = <1>; 178 io-channel-names = "parent"; 179 mux-controls = <&gpioA0mux>; 180 channels = "s0", "s1"; 181 }; 182 183 adc8mux: adc8mux { 184 compatible = "io-channel-mux"; 185 io-channels = <&adc 8>; 186 #io-channel-cells = <1>; 187 io-channel-names = "parent"; 188 mux-controls = <&gpioA0mux>; 189 channels = "s0", "s1"; 190 }; 191 192 adc9mux: adc9mux { 193 compatible = "io-channel-mux"; 194 io-channels = <&adc 9>; 195 #io-channel-cells = <1>; 196 io-channel-names = "parent"; 197 mux-controls = <&gpioA0mux>; 198 channels = "s0", "s1"; 199 }; 200 201 adc10mux: adc10mux { 202 compatible = "io-channel-mux"; 203 io-channels = <&adc 10>; 204 #io-channel-cells = <1>; 205 io-channel-names = "parent"; 206 mux-controls = <&gpioA0mux>; 207 channels = "s0", "s1"; 208 }; 209 210 adc11mux: adc11mux { 211 compatible = "io-channel-mux"; 212 io-channels = <&adc 11>; 213 #io-channel-cells = <1>; 214 io-channel-names = "parent"; 215 mux-controls = <&gpioA0mux>; 216 channels = "s0", "s1"; 217 }; 218 219 adc12mux: adc12mux { 220 compatible = "io-channel-mux"; 221 io-channels = <&adc 12>; 222 #io-channel-cells = <1>; 223 io-channel-names = "parent"; 224 mux-controls = <&gpioA0mux>; 225 channels = "s0", "s1"; 226 }; 227 228 adc13mux: adc13mux { 229 compatible = "io-channel-mux"; 230 io-channels = <&adc 13>; 231 #io-channel-cells = <1>; 232 io-channel-names = "parent"; 233 mux-controls = <&gpioA0mux>; 234 channels = "s0", "s1"; 235 }; 236 237 iio-hwmon { 238 compatible = "iio-hwmon"; 239 io-channels = <&adc0mux 0>, <&adc0mux 1>, 240 <&adc1mux 0>, <&adc1mux 1>, 241 <&adc2mux 0>, <&adc2mux 1>, 242 <&adc3mux 0>, <&adc3mux 1>, 243 <&adc4mux 0>, <&adc4mux 1>, 244 <&adc5mux 0>, <&adc5mux 1>, 245 <&adc6mux 0>, <&adc6mux 1>, 246 <&adc7mux 0>, <&adc7mux 1>, 247 <&adc8mux 0>, <&adc8mux 1>, 248 <&adc9mux 0>, <&adc9mux 1>, 249 <&adc10mux 0>, <&adc10mux 1>, 250 <&adc11mux 0>, <&adc11mux 1>, 251 <&adc12mux 0>, <&adc12mux 1>, 252 <&adc13mux 0>, <&adc13mux 1>, 253 <&adc 14>, <&adc 15>; 254 }; 255 }; 256 257 &fmc { 258 status = "okay"; 259 flash@0 { 260 status = "okay"; 261 m25p,fast-read; 262 label = "bmc"; 263 /* spi-max-frequency = <50000000>; */ 264 #include "openbmc-flash-layout-64.dtsi" 265 }; 266 267 flash@1 { 268 status = "okay"; 269 m25p,fast-read; 270 label = "alt-bmc"; 271 #include "openbmc-flash-layout-64-alt.dtsi" 272 }; 273 }; 274 275 &spi1 { 276 status = "okay"; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_spi1_default>; 279 280 flash@0 { 281 status = "okay"; 282 m25p,fast-read; 283 label = "pnor"; 284 /* spi-max-frequency = <100000000>; */ 285 partitions { 286 compatible = "fixed-partitions"; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 uefi@400000 { 290 reg = <0x400000 0x1C00000>; 291 label = "pnor-uefi"; 292 }; 293 }; 294 }; 295 }; 296 297 &uart1 { 298 status = "okay"; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_txd1_default 301 &pinctrl_rxd1_default 302 &pinctrl_ncts1_default 303 &pinctrl_nrts1_default>; 304 }; 305 306 &uart2 { 307 status = "okay"; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_txd2_default 310 &pinctrl_rxd2_default>; 311 }; 312 313 &uart3 { 314 status = "okay"; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_txd3_default 317 &pinctrl_rxd3_default>; 318 }; 319 320 &uart4 { 321 status = "okay"; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_txd4_default 324 &pinctrl_rxd4_default>; 325 }; 326 327 /* The BMC's uart */ 328 &uart5 { 329 status = "okay"; 330 }; 331 332 &mac0 { 333 status = "okay"; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_rmii1_default>; 336 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, 337 <&syscon ASPEED_CLK_MAC1RCLK>; 338 clock-names = "MACCLK", "RCLK"; 339 use-ncsi; 340 }; 341 342 &mac1 { 343 status = "okay"; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; 346 }; 347 348 &i2c0 { 349 status = "okay"; 350 ssif-bmc@10 { 351 compatible = "ssif-bmc"; 352 reg = <0x10>; 353 }; 354 }; 355 356 &i2c1 { 357 status = "okay"; 358 }; 359 360 &i2c2 { 361 status = "okay"; 362 smpro@4f { 363 compatible = "ampere,smpro"; 364 reg = <0x4f>; 365 }; 366 smpro@4e { 367 compatible = "ampere,smpro"; 368 reg = <0x4e>; 369 }; 370 }; 371 372 &i2c3 { 373 status = "okay"; 374 eeprom@50 { 375 compatible = "microchip,24c64", "atmel,24c64"; 376 reg = <0x50>; 377 pagesize = <32>; 378 }; 379 380 inlet_mem2: tmp175@28 { 381 compatible = "ti,tmp175"; 382 reg = <0x28>; 383 }; 384 385 inlet_cpu: tmp175@29 { 386 compatible = "ti,tmp175"; 387 reg = <0x29>; 388 }; 389 390 inlet_mem1: tmp175@2a { 391 compatible = "ti,tmp175"; 392 reg = <0x2a>; 393 }; 394 395 outlet_cpu: tmp175@2b { 396 compatible = "ti,tmp175"; 397 reg = <0x2b>; 398 }; 399 400 outlet1: tmp175@2c { 401 compatible = "ti,tmp175"; 402 reg = <0x2c>; 403 }; 404 405 outlet2: tmp175@2d { 406 compatible = "ti,tmp175"; 407 reg = <0x2d>; 408 }; 409 }; 410 411 &i2c4 { 412 status = "okay"; 413 rtc@51 { 414 compatible = "nxp,pcf85063a"; 415 reg = <0x51>; 416 }; 417 }; 418 419 &i2c5 { 420 status = "okay"; 421 i2c-mux@70 { 422 compatible = "nxp,pca9548"; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 reg = <0x70>; 426 i2c-mux-idle-disconnect; 427 428 ocpslot: i2c@0 { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 reg = <0x0>; 432 433 ocpslot_temp: temperature-sensor@1f { 434 compatible = "ti,tmp421"; 435 reg = <0x1f>; 436 }; 437 }; 438 439 nvmeslot_0_7: i2c@3 { 440 #address-cells = <1>; 441 #size-cells = <0>; 442 reg = <0x3>; 443 }; 444 }; 445 446 i2c-mux@71 { 447 compatible = "nxp,pca9548"; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 reg = <0x71>; 451 i2c-mux-idle-disconnect; 452 453 nvmeslot_8_15: i2c@4 { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 reg = <0x4>; 457 }; 458 459 nvmeslot_16_23: i2c@3 { 460 #address-cells = <1>; 461 #size-cells = <0>; 462 reg = <0x3>; 463 }; 464 465 }; 466 467 i2c-mux@72 { 468 compatible = "nxp,pca9545"; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 reg = <0x72>; 472 i2c-mux-idle-disconnect; 473 474 nvme_m2_0: i2c@0 { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 reg = <0x0>; 478 }; 479 480 nvme_m2_1: i2c@1 { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 reg = <0x1>; 484 }; 485 }; 486 }; 487 488 &nvmeslot_0_7 { 489 status = "okay"; 490 491 i2c-mux@75 { 492 compatible = "nxp,pca9548"; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 reg = <0x75>; 496 i2c-mux-idle-disconnect; 497 498 nvmeslot_0: i2c@0 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 reg = <0x0>; 502 }; 503 nvmeslot_1: i2c@1 { 504 #address-cells = <1>; 505 #size-cells = <0>; 506 reg = <0x1>; 507 }; 508 nvmeslot_2: i2c@2 { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 reg = <0x2>; 512 }; 513 nvmeslot_3: i2c@3 { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 reg = <0x3>; 517 }; 518 nvmeslot_4: i2c@4 { 519 #address-cells = <1>; 520 #size-cells = <0>; 521 reg = <0x4>; 522 }; 523 nvmeslot_5: i2c@5 { 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <0x5>; 527 }; 528 nvmeslot_6: i2c@6 { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 reg = <0x6>; 532 }; 533 nvmeslot_7: i2c@7 { 534 #address-cells = <1>; 535 #size-cells = <0>; 536 reg = <0x7>; 537 }; 538 539 }; 540 }; 541 542 &nvmeslot_8_15 { 543 status = "okay"; 544 545 i2c-mux@75 { 546 compatible = "nxp,pca9548"; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 reg = <0x75>; 550 i2c-mux-idle-disconnect; 551 552 nvmeslot_8: i2c@0 { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 reg = <0x0>; 556 }; 557 nvmeslot_9: i2c@1 { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 reg = <0x1>; 561 }; 562 nvmeslot_10: i2c@2 { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 reg = <0x2>; 566 }; 567 nvmeslot_11: i2c@3 { 568 #address-cells = <1>; 569 #size-cells = <0>; 570 reg = <0x3>; 571 }; 572 nvmeslot_12: i2c@4 { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 reg = <0x4>; 576 }; 577 nvmeslot_13: i2c@5 { 578 #address-cells = <1>; 579 #size-cells = <0>; 580 reg = <0x5>; 581 }; 582 nvmeslot_14: i2c@6 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 reg = <0x6>; 586 }; 587 nvmeslot_15: i2c@7 { 588 #address-cells = <1>; 589 #size-cells = <0>; 590 reg = <0x7>; 591 }; 592 }; 593 }; 594 595 &nvmeslot_16_23 { 596 status = "okay"; 597 598 i2c-mux@75 { 599 compatible = "nxp,pca9548"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 reg = <0x75>; 603 i2c-mux-idle-disconnect; 604 605 nvmeslot_16: i2c@0 { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 reg = <0x0>; 609 }; 610 nvmeslot_17: i2c@1 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 reg = <0x1>; 614 }; 615 nvmeslot_18: i2c@2 { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 reg = <0x2>; 619 }; 620 nvmeslot_19: i2c@3 { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 reg = <0x3>; 624 }; 625 nvmeslot_20: i2c@4 { 626 #address-cells = <1>; 627 #size-cells = <0>; 628 reg = <0x4>; 629 }; 630 nvmeslot_21: i2c@5 { 631 #address-cells = <1>; 632 #size-cells = <0>; 633 reg = <0x5>; 634 }; 635 nvmeslot_22: i2c@6 { 636 #address-cells = <1>; 637 #size-cells = <0>; 638 reg = <0x6>; 639 }; 640 nvmeslot_23: i2c@7 { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 reg = <0x7>; 644 }; 645 }; 646 }; 647 648 &i2c6 { 649 status = "okay"; 650 psu@58 { 651 compatible = "pmbus"; 652 reg = <0x58>; 653 }; 654 655 psu@59 { 656 compatible = "pmbus"; 657 reg = <0x59>; 658 }; 659 }; 660 661 &i2c7 { 662 status = "okay"; 663 }; 664 665 &i2c8 { 666 status = "okay"; 667 }; 668 669 &i2c9 { 670 status = "okay"; 671 }; 672 673 &i2c10 { 674 status = "okay"; 675 adm1278@10 { 676 compatible = "adi,adm1278"; 677 reg = <0x10>; 678 }; 679 680 adm1278@11 { 681 compatible = "adi,adm1278"; 682 reg = <0x11>; 683 }; 684 }; 685 686 &gfx { 687 status = "okay"; 688 memory-region = <&gfx_memory>; 689 }; 690 691 &pwm_tacho { 692 status = "okay"; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default 695 &pinctrl_pwm4_default &pinctrl_pwm5_default 696 &pinctrl_pwm6_default &pinctrl_pwm7_default>; 697 698 fan@0 { 699 reg = <0x02>; 700 aspeed,fan-tach-ch = /bits/ 8 <0x04>; 701 }; 702 703 fan@1 { 704 reg = <0x02>; 705 aspeed,fan-tach-ch = /bits/ 8 <0x05>; 706 }; 707 708 fan@2 { 709 reg = <0x03>; 710 aspeed,fan-tach-ch = /bits/ 8 <0x06>; 711 }; 712 713 fan@3 { 714 reg = <0x03>; 715 aspeed,fan-tach-ch = /bits/ 8 <0x07>; 716 }; 717 718 fan@4 { 719 reg = <0x04>; 720 aspeed,fan-tach-ch = /bits/ 8 <0x08>; 721 }; 722 723 fan@5 { 724 reg = <0x04>; 725 aspeed,fan-tach-ch = /bits/ 8 <0x09>; 726 }; 727 728 fan@6 { 729 reg = <0x05>; 730 aspeed,fan-tach-ch = /bits/ 8 <0x0a>; 731 }; 732 733 fan@7 { 734 reg = <0x05>; 735 aspeed,fan-tach-ch = /bits/ 8 <0x0b>; 736 }; 737 738 fan@8 { 739 reg = <0x06>; 740 aspeed,fan-tach-ch = /bits/ 8 <0x0c>; 741 }; 742 743 fan@9 { 744 reg = <0x06>; 745 aspeed,fan-tach-ch = /bits/ 8 <0x0d>; 746 }; 747 748 fan@10 { 749 reg = <0x07>; 750 aspeed,fan-tach-ch = /bits/ 8 <0x0e>; 751 }; 752 753 fan@11 { 754 reg = <0x07>; 755 aspeed,fan-tach-ch = /bits/ 8 <0x0f>; 756 }; 757 758 }; 759 760 &vhub { 761 status = "okay"; 762 }; 763 764 &adc { 765 status = "okay"; 766 }; 767 768 &video { 769 status = "okay"; 770 memory-region = <&video_engine_memory>; 771 }; 772 773 &gpio { 774 gpio-line-names = 775 /*A0-A7*/ "","","","host0-special-boot","","","","", 776 /*B0-B7*/ "i2c-backup-sel","","","", 777 "power-button","presence-cpu0","","", 778 /*C0-C7*/ "","","","","","","","", 779 /*D0-D7*/ "","","","","","","","", 780 /*E0-E7*/ "","","","","","","","", 781 /*F0-F7*/ "ps0-pgood","ps1-pgood","power-chassis-control","s0-ddr-save", 782 "power-chassis-good", "s1-ddr-save","","", 783 /*G0-G7*/ "host0-ready","host0-shd-req-n","host0-shd-ack-n", 784 "s0-overtemp-n","","","","", 785 /*H0-H7*/ "uart1-mode1","uart2-mode1","uart3-mode1","uart4-mode1", 786 "ps0-vin-good","ps1-vin-good","","i2c6-reset-n", 787 /*I0-I7*/ "presence-ps0","presence-ps1","s1-special-boot","","","","","", 788 /*J0-J7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", 789 "host0-reboot-ack-n","","","","", 790 /*K0-K7*/ "","","","","","","","", 791 /*L0-L7*/ "","","","host0-sysreset-n","s0-spi-auth-fail-n","","","", 792 /*M0-M7*/ "","","","","s0-i2c9-alert-n","s1-i2c9-alert-n","","", 793 /*N0-N7*/ "","","","","","","","", 794 /*O0-O7*/ "","","","","","","","", 795 /*P0-P7*/ "","","","","","","","", 796 /*Q0-Q7*/ "","","","","","identify-button","led-identify","", 797 /*R0-R7*/ "","","ext-hightemp-n","","ocp-main-pwren","reset-button","","", 798 /*S0-S7*/ "s0-vr-hot-n","s1-vr-hot-n","","", 799 "rtc-battery-voltage-read-enable","vr-pmbus-sel-n","","", 800 /*T0-T7*/ "","","","","","","","", 801 /*U0-U7*/ "","","","","","","","", 802 /*V0-V7*/ "","","","","","","","", 803 /*W0-W7*/ "","","","","","","","", 804 /*X0-X7*/ "","","","","","","","", 805 /*Y0-Y7*/ "","","","bmc-vga-en-n","","","","", 806 /*Z0-Z7*/ "s0-plimit","s1-fault-alert","s1-fw-boot-ok","s0-rtc-lock","", 807 "s1-sys-auth-failure-n","s1-overtemp-n","", 808 /*AA0-AA7*/ "","","","","","","","", 809 /*AB0-AB7*/ "s1-hightemp-n","s1-plimit","s0-ddr-addr","s1-ddr-addr","","", 810 "","", 811 /*AC0-AC7*/ "sys-pwr-gd","","spi0-program-sel","spi0-backup-sel","bmc-ok", 812 "","presence-cpu1","ocp-pgood"; 813 814 i2c4-o-en-hog { 815 gpio-hog; 816 gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; 817 output-high; 818 line-name = "i2c4-o-en"; 819 }; 820 821 ocp-aux-pwren-hog { 822 gpio-hog; 823 gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; 824 output-high; 825 line-name = "ocp-aux-pwren"; 826 }; 827 828 bmc-ready { 829 gpio-hog; 830 gpios = <ASPEED_GPIO(AC, 5) GPIO_ACTIVE_HIGH>; 831 output-high; 832 line-name = "bmc-ready"; 833 }; 834 };
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