1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2019 Facebook Inc.
3 /dts-v1/;
4
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include "ast2500-facebook-netbmc-common.dtsi"
7
8 / {
9 model = "Facebook Wedge 400 BMC";
10 compatible = "facebook,wedge400-bmc", "aspeed,ast2500";
11
12 aliases {
13 /*
14 * PCA9548 (2-0070) provides 8 channels connecting to
15 * SCM (System Controller Module).
16 */
17 i2c16 = &imux16;
18 i2c17 = &imux17;
19 i2c18 = &imux18;
20 i2c19 = &imux19;
21 i2c20 = &imux20;
22 i2c21 = &imux21;
23 i2c22 = &imux22;
24 i2c23 = &imux23;
25
26 /*
27 * PCA9548 (8-0070) provides 8 channels connecting to
28 * SMB (Switch Main Board).
29 */
30 i2c24 = &imux24;
31 i2c25 = &imux25;
32 i2c26 = &imux26;
33 i2c27 = &imux27;
34 i2c28 = &imux28;
35 i2c29 = &imux29;
36 i2c30 = &imux30;
37 i2c31 = &imux31;
38
39 /*
40 * PCA9548 (11-0076) provides 8 channels connecting to
41 * FCM (Fan Controller Module).
42 */
43 i2c32 = &imux32;
44 i2c33 = &imux33;
45 i2c34 = &imux34;
46 i2c35 = &imux35;
47 i2c36 = &imux36;
48 i2c37 = &imux37;
49 i2c38 = &imux38;
50 i2c39 = &imux39;
51
52 spi2 = &spi_gpio;
53 };
54
55 chosen {
56 stdout-path = &uart1;
57 bootargs = "console=ttyS0,9600n8 root=/dev/ram rw";
58 };
59
60 ast-adc-hwmon {
61 compatible = "iio-hwmon";
62 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>,
63 <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>;
64 };
65
66 /*
67 * GPIO-based SPI Master is required to access SPI TPM, because
68 * full-duplex SPI transactions are not supported by ASPEED SPI
69 * Controllers.
70 */
71 spi_gpio: spi {
72 status = "okay";
73 compatible = "spi-gpio";
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>;
78 gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
79 gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
80 gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
81 num-chipselects = <1>;
82
83 tpm@0 {
84 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
85 spi-max-frequency = <33000000>;
86 reg = <0>;
87 };
88 };
89 };
90
91 /*
92 * Both firmware flashes are 128MB on Wedge400 BMC.
93 */
94 &fmc_flash0 {
95 #include "facebook-bmc-flash-layout-128.dtsi"
96 };
97
98 &fmc_flash1 {
99 partitions {
100 compatible = "fixed-partitions";
101 #address-cells = <1>;
102 #size-cells = <1>;
103
104 flash1@0 {
105 reg = <0x0 0x8000000>;
106 label = "flash1";
107 };
108 };
109 };
110
111 &uart2 {
112 status = "okay";
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_txd2_default
115 &pinctrl_rxd2_default>;
116 };
117
118 &uart4 {
119 status = "okay";
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_txd4_default
122 &pinctrl_rxd4_default>;
123 };
124
125 /*
126 * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC
127 * communication.
128 */
129 &i2c0 {
130 status = "okay";
131 multi-master;
132 bus-frequency = <1000000>;
133 };
134
135 &i2c1 {
136 status = "okay";
137 };
138
139 &i2c2 {
140 status = "okay";
141
142 i2c-mux@70 {
143 compatible = "nxp,pca9548";
144 #address-cells = <1>;
145 #size-cells = <0>;
146 reg = <0x70>;
147 i2c-mux-idle-disconnect;
148
149 imux16: i2c@0 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 reg = <0>;
153 };
154
155 imux17: i2c@1 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 reg = <1>;
159 };
160
161 imux18: i2c@2 {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 reg = <2>;
165 };
166
167 imux19: i2c@3 {
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <3>;
171 };
172
173 imux20: i2c@4 {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 reg = <4>;
177 };
178
179 imux21: i2c@5 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 reg = <5>;
183 };
184
185 imux22: i2c@6 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 reg = <6>;
189 };
190
191 imux23: i2c@7 {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 reg = <7>;
195 };
196 };
197 };
198
199 &i2c3 {
200 status = "okay";
201 };
202
203 &i2c4 {
204 status = "okay";
205 };
206
207 &i2c5 {
208 status = "okay";
209 };
210
211 &i2c6 {
212 status = "okay";
213 };
214
215 &i2c7 {
216 status = "okay";
217 };
218
219 &i2c8 {
220 status = "okay";
221
222 i2c-mux@70 {
223 compatible = "nxp,pca9548";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <0x70>;
227 i2c-mux-idle-disconnect;
228
229 imux24: i2c@0 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 reg = <0>;
233 };
234
235 imux25: i2c@1 {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 reg = <1>;
239 };
240
241 imux26: i2c@2 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 reg = <2>;
245 };
246
247 imux27: i2c@3 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 reg = <3>;
251 };
252
253 imux28: i2c@4 {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 reg = <4>;
257 };
258
259 imux29: i2c@5 {
260 #address-cells = <1>;
261 #size-cells = <0>;
262 reg = <5>;
263 };
264
265 imux30: i2c@6 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 reg = <6>;
269 };
270
271 imux31: i2c@7 {
272 #address-cells = <1>;
273 #size-cells = <0>;
274 reg = <7>;
275 };
276
277 };
278 };
279
280 &i2c9 {
281 status = "okay";
282 };
283
284 &i2c10 {
285 status = "okay";
286 };
287
288 &i2c11 {
289 status = "okay";
290
291 i2c-mux@76 {
292 compatible = "nxp,pca9548";
293 #address-cells = <1>;
294 #size-cells = <0>;
295 reg = <0x76>;
296 i2c-mux-idle-disconnect;
297
298 imux32: i2c@0 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 reg = <0>;
302 };
303
304 imux33: i2c@1 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 reg = <1>;
308 };
309
310 imux34: i2c@2 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <2>;
314 };
315
316 imux35: i2c@3 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 reg = <3>;
320 };
321
322 imux36: i2c@4 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 reg = <4>;
326 };
327
328 imux37: i2c@5 {
329 #address-cells = <1>;
330 #size-cells = <0>;
331 reg = <5>;
332 };
333
334 imux38: i2c@6 {
335 #address-cells = <1>;
336 #size-cells = <0>;
337 reg = <6>;
338 };
339
340 imux39: i2c@7 {
341 #address-cells = <1>;
342 #size-cells = <0>;
343 reg = <7>;
344 };
345
346 };
347 };
348
349 &i2c12 {
350 status = "okay";
351 };
352
353 &i2c13 {
354 status = "okay";
355 };
356
357 &adc {
358 status = "okay";
359 };
360
361 &ehci1 {
362 status = "okay";
363 };
364
365 &uhci {
366 status = "okay";
367 };
368
369 &sdhci1 {
370 max-frequency = <25000000>;
371 /*
372 * DMA mode needs to be disabled to avoid conflicts with UHCI
373 * Controller in AST2500 SoC.
374 */
375 sdhci-caps-mask = <0x0 0x580000>;
376 };
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