1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // Copyright 2022 Quanta Corp.
3 /dts-v1/;
4
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/i2c/i2c.h>
8
9 / {
10 model = "Quanta S6Q BMC";
11 compatible = "quanta,s6q-bmc", "aspeed,ast2600";
12
13 aliases {
14 // bus 0
15 i2c20 = &SMB_HOST_DB2000_3V3AUX_SCL;
16 i2c21 = &U12_PCA9546_CH1;
17 i2c22 = &SMB_HOST_DB800_B_SCL;
18 i2c23 = &SMB_HOST_DB800_C_SCL;
19
20 // bus 1
21 i2c24 = &SMB_M2_P0_1V8AUX_SCL;
22 i2c25 = &SMB_M2_P1_1V8AUX_SCL;
23 i2c26 = &SMB_CPU_PIROM_3V3AUX_SCL;
24 i2c27 = &SMB_TEMP_3V3AUX_SCL;
25 i2c28 = &SMB_IPMB_3V3AUX_SSDSB_SCL;
26 i2c29 = &SMB_IPMB_3V3AUX_SCL;
27 i2c31 = &SMB_FB_SCL;
28
29 // bus 1 - Fan board
30 i2c32 = &SMB_IOEXP_SCL;
31 i2c33 = &SMB_PROGRAM_SCL;
32 i2c34 = &SMB_FB_SCL_CH2;
33 i2c35 = &SMB_FAN_SENSE_SCL;
34
35 // bus 6
36 i2c36 = &U197_PCA9546_CH0;
37 i2c37 = &U197_PCA9546_CH1;
38 i2c38 = &U197_PCA9546_CH2;
39 i2c39 = &U197_PCA9546_CH3;
40
41 //bus 7
42 i2c40 = &SMB_OCP_SFF_3V3AUX_SCL; //OCP1
43 i2c41 = &SMB_OCP_LFF_3V3AUX_SCL; //OCP2
44 };
45
46 chosen {
47 stdout-path = &uart5;
48 bootargs = "console=ttyS4,115200n8 earlycon";
49 };
50
51 memory@80000000 {
52 device_type = "memory";
53 reg = <0x80000000 0x40000000>;
54 };
55
56 iio-hwmon {
57 compatible = "iio-hwmon";
58 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
59 <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
60 <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
61 <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
62 };
63
64 leds {
65 compatible = "gpio-leds";
66
67 BMC_HEARTBEAT_N {
68 label = "BMC_HEARTBEAT_N";
69 gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
70 linux,default-trigger = "heartbeat";
71 };
72
73 BMC_LED_STATUS_AMBER_N {
74 label = "BMC_LED_STATUS_AMBER_N";
75 gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>;
76 default-state = "off";
77 };
78
79 FM_ID_LED_N {
80 label = "FM_ID_LED_N";
81 gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>;
82 default-state = "off";
83 };
84 };
85 };
86
87 &gpio0 {
88 gpio-line-names =
89 /*A0 - A7*/ "", "", "", "", "", "", "", "",
90 /*B0 - B7*/ "", "", "", "", "", "", "", "",
91 /*C0 - C7*/ "", "", "", "", "", "", "", "",
92 /*D0 - D7*/ "", "", "", "", "", "", "", "",
93 /*E0 - E7*/ "", "", "", "", "", "", "", "",
94 /*F0 - F7*/ "PLTRST_N", "", "PWR_DEBUG_N", "", "", "", "", "",
95 /*G0 - G7*/ "", "", "", "", "", "", "", "",
96 /*H0 - H7*/ "", "", "", "", "", "", "", "",
97 /*I0 - I7*/ "", "", "", "", "", "", "", "",
98 /*J0 - J7*/ "", "", "", "", "", "", "", "",
99 /*K0 - K7*/ "", "", "", "", "", "", "", "",
100 /*L0 - L7*/ "", "", "", "", "PREQ_N", "TCK_MUX_SEL", "", "",
101 /*M0 - M7*/ "", "", "", "PWRGD_SYS_PWROK", "", "PRDY_N", "", "",
102 /*N0 - N7*/ "", "", "", "", "", "", "", "",
103 /*O0 - O7*/ "", "", "", "", "", "", "", "",
104 /*P0 - P7*/ "SYS_BMC_PWRBTN_R_N", "SYS_PWRBTN_N", "FM_MB_RST_BTN", "RST_BMC_RSTBTN_OUT_N", "", "", "", "",
105 /*Q0 - Q7*/ "", "", "", "", "", "", "", "",
106 /*R0 - R7*/ "", "", "", "", "", "", "", "",
107 /*S0 - S7*/ "", "", "", "FP_ID_BTN_SCM_N", "", "", "", "",
108 /*T0 - T7*/ "", "", "", "", "", "", "", "",
109 /*U0 - U7*/ "", "", "", "", "", "", "", "",
110 /*V0 - V7*/ "", "", "", "", "", "SMI", "", "",
111 /*W0 - W7*/ "", "", "", "", "", "", "", "",
112 /*X0 - X7*/ "", "", "", "", "", "", "", "",
113 /*Y0 - Y7*/ "", "", "", "", "", "", "", "",
114 /*Z0 - Z7*/ "FM_BMC_READY_N", "", "", "", "", "", "", "",
115 /*AA0 - AA7*/ "", "", "", "", "", "", "", "",
116 /*AB0 - AB7*/ "", "", "", "", "", "", "", "",
117 /*AC0 - AC7*/ "", "", "", "", "", "", "", "";
118 };
119
120 &sgpiom0 {
121 status = "okay";
122 ngpios = <128>;
123 bus-frequency = <48000>;
124 gpio-line-names =
125 /* SGPIO input lines */
126 /*IOA0-IOA7*/ "","", "SIO_POWER_GOOD","OA1", "XDP_PRST_N","", "","", "FM_SLPS3_PLD_N","", "FM_SLPS4_PLD_N","", "FM_BIOS_POST_CMPLT_BMC_N","", "FM_ADR_TRIGGER_N","OA7",
127 /*IOB0-IOB7*/ "FM_ADR_COMPLETE","", "FM_PMBUS_ALERT_B_EN","", "PSU0_PRESENT_N","", "PSU1_PRESENT_N","", "PSU0_VIN_BUF_GOOD","", "PSU01_VIN_BUF_GOOD","", "PWRGD_PS0_PWROK_R","", "PWRGD_PS1_PWROK_R","",
128 /*IOC0-IOC7*/ "PWRGD_PS_PWROK_PLD_R","", "CHASSIS_INTRUSION","", "BMC_MFG_MODE","", "FM_BMC_EN_DET_R","", "FM_ME_BT_DONE","", "CPU1_PRESENCE","", "CPU2_PRESENCE","", "IRQ_PSYS_CRIT_N","",
129 /*IOD0-IOD7*/ "","", "CPU1_THERMTRIP","", "CPU2_THERMTRIP","", "CPU1_MEM_THERM_EVENT","", "CPU2_MEM_THERM_EVENT","", "CPU1_VRHOT","", "CPU2_VRHOT","", "","",
130 /*IOE0-IOE7*/ "","", "CPU1_MEM_VRHOT","", "CPU2_MEM_VRHOT","", "","", "PCH_BMC_THERMTRIP","", "","", "","", "","",
131 /*IOF0-IOF7*/ "CPU_ERR0","", "CPU_ERR1","", "CPU_ERR2","", "","", "","", "CPU_CATERR","", "","", "","",
132 /*IOG0-IOG7*/ "","", "","", "","", "","", "","", "","", "","", "","",
133 /*IOH0-IOH7*/ "","", "FP_ID_BTN_R1_N","", "FP_RST_BTN_N","", "","", "","", "FP_PWR_BTN_PLD_N_R","", "","", "","",
134 /*IOI0-IOI7*/ "","", "","", "","", "","", "","", "","", "","", "","",
135 /*IOJ0-IOJ7*/ "","", "","", "","", "","", "","", "","", "","", "","",
136 /*IOK0-IOK7*/ "","", "","", "","", "","", "","", "","", "","", "","",
137 /*IOL0-IOL7*/ "","", "","", "","", "","", "","", "","", "","", "","",
138 /*IOM0-IOM7*/ "","", "","", "","", "","", "","", "","", "","", "","",
139 /*ION0-ION7*/ "","BMC_SW_HEARTBEAT_N_R", "","FP_LED_FAULT_N", "","FP_ID_LED_N", "","FM_BMC_RSTBTN_OUT_N", "","FM_THERMTRIP_DLY_LVC1_R_N", "","", "","RST_PCA9548_SENSOR_PLD_N", "","USB_OC1_REAR_N",
140 /*IOO0-IOO7*/ "","IRQ_TPM_SPI_N", "","", "","IRQ_PCH_SCI_WHEA_R_N", "","IRQ_BMC_PCH_NMI_R", "","H_CPU_NMI_LVC1_R_N", "","", "","", "","FM_JTAG_BMC_PLD_MUX_SEL",
141 /*IOP0-IOP7*/ "IP0","OP0", "","", "","", "","", "","", "","", "","", "IP7","OP7";
142 };
143
144 &adc0 {
145 vref = <2500>;
146 status = "okay";
147
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
150 &pinctrl_adc2_default &pinctrl_adc3_default
151 &pinctrl_adc4_default &pinctrl_adc5_default
152 &pinctrl_adc6_default &pinctrl_adc7_default>;
153 };
154
155 &adc1 {
156 vref = <2500>;
157 status = "okay";
158
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
161 &pinctrl_adc10_default &pinctrl_adc11_default
162 &pinctrl_adc12_default &pinctrl_adc13_default
163 &pinctrl_adc14_default &pinctrl_adc15_default>;
164 };
165
166 &mdio2 {
167 status = "okay";
168
169 ethphy2: ethernet-phy@0 {
170 compatible = "ethernet-phy-ieee802.3-c22";
171 reg = <0>;
172 };
173 };
174
175 &mac2 {
176 status = "okay";
177
178 phy-mode = "rgmii";
179 phy-handle = <ðphy2>;
180
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_rgmii3_default>;
183 };
184
185 &mac3 {
186 status = "okay";
187
188 phy-mode = "rmii";
189 use-ncsi;
190
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_rmii4_default>;
193 };
194
195 &fmc {
196 status = "okay";
197
198 flash@0 {
199 status = "okay";
200 m25p,fast-read;
201 label = "bmc";
202 spi-max-frequency = <50000000>;
203 #include "openbmc-flash-layout-64.dtsi"
204 };
205 };
206
207 &spi2 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
210 &pinctrl_spi2cs2_default>;
211 status = "okay";
212
213 flash@0 {
214 status = "okay";
215 m25p,fast-read;
216 label = "spi2:0";
217 spi-max-frequency = <50000000>;
218 };
219 };
220
221 &kcs1 {
222 status = "okay";
223 aspeed,lpc-io-reg = <0xCA0>;
224 };
225
226 &kcs2 {
227 status = "okay";
228 aspeed,lpc-io-reg = <0xCA8>;
229 };
230
231 &kcs3 {
232 status = "okay";
233 aspeed,lpc-io-reg = <0xCA2>;
234 };
235
236 &emmc_controller {
237 status = "okay";
238 };
239
240 &emmc {
241 non-removable;
242 bus-width = <4>;
243 max-frequency = <100000000>;
244 };
245
246 &vhub {
247 status = "okay";
248 };
249
250 &lpc_snoop {
251 status = "okay";
252 snoop-ports = <0x80>;
253 };
254
255 &uart1 {
256 status = "okay";
257 };
258
259 &uart2 {
260 status = "okay";
261 };
262
263 &uart4 {
264 status = "okay";
265 };
266
267 &uart5 {
268 status = "okay";
269 };
270
271 &uart_routing {
272 status = "okay";
273 };
274
275 &i2c0 {
276 status = "okay";
277
278 U34_PWR_ADC@48 {
279 compatible = "ti,ads7830";
280 reg = <0x48>;
281 };
282
283 U35_PWR_ADC@4b {
284 compatible = "ti,ads7830";
285 reg = <0x4b>;
286 };
287
288 i2c-mux@70 {
289 compatible = "nxp,pca9546";
290 reg = <0x70>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 i2c-mux-idle-disconnect;
294
295 SMB_HOST_DB2000_3V3AUX_SCL: i2c@0 {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 reg = <0>;
299 };
300
301 U12_PCA9546_CH1: i2c@1 {
302 #address-cells = <1>;
303 #size-cells = <0>;
304 reg = <1>;
305 };
306
307 SMB_HOST_DB800_B_SCL: i2c@2 {
308 #address-cells = <1>;
309 #size-cells = <0>;
310 reg = <2>;
311 };
312
313 SMB_HOST_DB800_C_SCL: i2c@3 {
314 #address-cells = <1>;
315 #size-cells = <0>;
316 reg = <3>;
317 };
318 };
319 };
320
321 &i2c1 {
322 status = "okay";
323
324 i2c-mux@59 {
325 compatible = "nxp,pca9848";
326 reg = <0x59>;
327 #address-cells = <1>;
328 #size-cells = <0>;
329 i2c-mux-idle-disconnect;
330
331 SMB_M2_P0_1V8AUX_SCL: i2c@0 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 reg = <0>;
335 };
336
337 SMB_M2_P1_1V8AUX_SCL: i2c@1 {
338 #address-cells = <1>;
339 #size-cells = <0>;
340 reg = <1>;
341 };
342
343 SMB_CPU_PIROM_3V3AUX_SCL: i2c@2 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 reg = <2>;
347 };
348
349 SMB_TEMP_3V3AUX_SCL: i2c@3 {
350 #address-cells = <1>;
351 #size-cells = <0>;
352 reg = <3>;
353
354 U163_tmp75@48 {
355 compatible = "ti,tmp75";
356 reg = <0x48>;
357 };
358 U114_tmp75@49 {
359 compatible = "ti,tmp75";
360 reg = <0x49>;
361 };
362 };
363
364 SMB_IPMB_3V3AUX_SSDSB_SCL: i2c@4 {
365 #address-cells = <1>;
366 #size-cells = <0>;
367 reg = <4>;
368
369 U4_tmp75@4c {
370 compatible = "ti,tmp75";
371 reg = <0x4c>;
372 };
373 U73_tmp75@4d {
374 compatible = "ti,tmp75";
375 reg = <0x4d>;
376 };
377 };
378
379 SMB_IPMB_3V3AUX_SCL: i2c@5 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 reg = <5>;
383
384 U190_fru@51 {
385 compatible = "atmel,24c128";
386 reg = <0x51>;
387 pagesize = <32>;
388 };
389 };
390
391 SMB_FB_SCL: i2c@7 {
392 #address-cells = <1>;
393 #size-cells = <0>;
394 reg = <7>;
395
396 i2c-mux@77 {
397 compatible = "nxp,pca9546";
398 reg = <0x77>;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 i2c-mux-idle-disconnect;
402
403 SMB_IOEXP_SCL: i2c@0 {
404 #address-cells = <1>;
405 #size-cells = <0>;
406 reg = <0>;
407 };
408
409 SMB_PROGRAM_SCL: i2c@1 {
410 #address-cells = <1>;
411 #size-cells = <0>;
412 reg = <1>;
413 };
414
415 SMB_FB_SCL_CH2: i2c@2 {
416 #address-cells = <1>;
417 #size-cells = <0>;
418 reg = <2>;
419 };
420
421 SMB_FAN_SENSE_SCL: i2c@3 {
422 #address-cells = <1>;
423 #size-cells = <0>;
424 reg = <3>;
425
426 Current_Meter_U2@45 {
427 compatible = "ti,ina219";
428 reg = <0x45>;
429 shunt-resistor = <1000>; /* = 1 mOhm */
430 };
431
432 Current_Meter_U3@44 {
433 compatible = "ti,ina219";
434 reg = <0x44>;
435 shunt-resistor = <1000>; /* = 1 mOhm */
436 };
437
438 TEMP_sensor_U2@4b {
439 compatible = "ti,tmp75";
440 reg = <0x4b>;
441 };
442 };
443 };
444 };
445 };
446 };
447
448 &i2c2 {
449 status = "okay";
450 bus-frequency = <400000>;
451
452 ipmb@10 {
453 compatible = "ipmb-dev";
454 reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
455 i2c-protocol;
456 };
457 };
458
459 &i2c3 {
460 status = "okay";
461
462 /* MB FRU (U173) @ 0xA2 */
463 mb_fru: mb_fru@51 {
464 compatible = "atmel,24c128";
465 reg = <0x51>;
466 pagesize = <32>;
467 };
468
469 /* FP_U1 Inlet */
470 FP_U1_tmp75@4a {
471 compatible = "ti,tmp75";
472 reg = <0x4a>;
473 };
474
475 FP_U4_fru@52 {
476 compatible = "atmel,24c02";
477 reg = <0x52>;
478 pagesize = <16>;
479 };
480 };
481
482 &i2c4 {
483 status = "okay";
484 };
485
486 &i2c5 {
487 status = "okay";
488 };
489
490 &i2c6 {
491 status = "okay";
492
493 i2c-mux@77 {
494 compatible = "nxp,pca9548";
495 #address-cells = <1>;
496 #size-cells = <0>;
497 reg = <0x77>;
498 i2c-mux-idle-disconnect;
499
500 U197_PCA9546_CH0: i2c@0 {
501 #address-cells = <1>;
502 #size-cells = <0>;
503 reg = <0>;
504 };
505
506 U197_PCA9546_CH1: i2c@1 {
507 #address-cells = <1>;
508 #size-cells = <0>;
509 reg = <1>;
510
511 cpu0_pvccin@60 {
512 compatible = "isil,raa229004";
513 reg = <0x60>;
514 };
515
516 cpu0_pvccinfaon@61 {
517 compatible = "isil,isl69260";
518 reg = <0x61>;
519 };
520
521 cpu0_pvccd_hv@63 {
522 compatible = "isil,isl69260";
523 reg = <0x63>;
524 };
525 };
526
527 U197_PCA9546_CH2: i2c@2 {
528 #address-cells = <1>;
529 #size-cells = <0>;
530 reg = <2>;
531
532 cpu1_pvccin@72 {
533 compatible = "isil,raa229004";
534 reg = <0x72>;
535 };
536
537 cpu1_pvccinfaon@74 {
538 compatible = "isil,isl69260";
539 reg = <0x74>;
540 };
541
542 cpu1_pvccd_hv@76 {
543 compatible = "isil,isl69260";
544 reg = <0x76>;
545 };
546 };
547
548 U197_PCA9546_CH3: i2c@3 {
549 #address-cells = <1>;
550 #size-cells = <0>;
551 reg = <3>;
552 };
553 };
554 };
555
556 &i2c7 {
557 status = "okay";
558
559 i2c-mux@75 {
560 compatible = "nxp,pca9546";
561 #address-cells = <1>;
562 #size-cells = <0>;
563 reg = <0x75>;
564 i2c-mux-idle-disconnect;
565
566 SMB_OCP_SFF_3V3AUX_SCL: i2c@0 {
567 #address-cells = <1>;
568 #size-cells = <0>;
569 reg = <0>;
570 };
571
572 SMB_OCP_LFF_3V3AUX_SCL: i2c@1 {
573 #address-cells = <1>;
574 #size-cells = <0>;
575 reg = <1>;
576 };
577 };
578 };
579
580 &i2c8 {
581 status = "okay";
582 };
583
584 &i2c9 {
585 status = "okay";
586 };
587
588 &i2c11 {
589 status = "okay";
590 };
591
592 &i2c14 {
593 status = "okay";
594
595 /* SCM FRU (U19) @ 0xA2 */
596 scm_fru: scm_fru@51 {
597 compatible = "atmel,24c128";
598 reg = <0x51>;
599 pagesize = <32>;
600 };
601
602 scm_tmp75_u4@4a {
603 compatible = "ti,tmp75";
604 reg = <0x4a>;
605 };
606 };
607
608 &i2c15 {
609 status = "okay";
610 };
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