1 /*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
36
37 / {
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
43
44 aliases {
45 serial0 = &uart0;
46 serial1 = &uart1;
47 ethernet0 = &amac0;
48 ethernet1 = &amac1;
49 ethernet2 = &amac2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 cpu0: cpu@0 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
60 reg = <0x0>;
61 };
62
63 cpu1: cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a9";
66 next-level-cache = <&L2>;
67 enable-method = "brcm,bcm-nsp-smp";
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
70 };
71 };
72
73 pmu {
74 compatible = "arm,cortex-a9-pmu";
75 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-affinity = <&cpu0>, <&cpu1>;
78 };
79
80 mpcore-bus@19000000 {
81 compatible = "simple-bus";
82 ranges = <0x00000000 0x19000000 0x00023000>;
83 #address-cells = <1>;
84 #size-cells = <1>;
85
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
88 compatible = "brcm,nsp-armpll";
89 clocks = <&osc>;
90 reg = <0x00000 0x1000>;
91 };
92
93 timer@20200 {
94 compatible = "arm,cortex-a9-global-timer";
95 reg = <0x20200 0x100>;
96 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
97 clocks = <&periph_clk>;
98 };
99
100 twd-timer@20600 {
101 compatible = "arm,cortex-a9-twd-timer";
102 reg = <0x20600 0x20>;
103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_EDGE_RISING)>;
105 clocks = <&periph_clk>;
106 };
107
108 twd-watchdog@20620 {
109 compatible = "arm,cortex-a9-twd-wdt";
110 reg = <0x20620 0x20>;
111 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
112 IRQ_TYPE_LEVEL_HIGH)>;
113 clocks = <&periph_clk>;
114 };
115
116 gic: interrupt-controller@21000 {
117 compatible = "arm,cortex-a9-gic";
118 #interrupt-cells = <3>;
119 #address-cells = <0>;
120 interrupt-controller;
121 reg = <0x21000 0x1000>,
122 <0x20100 0x100>;
123 };
124
125 L2: cache-controller@22000 {
126 compatible = "arm,pl310-cache";
127 reg = <0x22000 0x1000>;
128 cache-unified;
129 cache-level = <2>;
130 };
131 };
132
133 clocks {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 ranges;
137
138 osc: oscillator {
139 #clock-cells = <0>;
140 compatible = "fixed-clock";
141 clock-frequency = <25000000>;
142 };
143
144 iprocmed: iprocmed {
145 #clock-cells = <0>;
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
148 clock-div = <2>;
149 clock-mult = <1>;
150 };
151
152 iprocslow: iprocslow {
153 #clock-cells = <0>;
154 compatible = "fixed-factor-clock";
155 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
156 clock-div = <4>;
157 clock-mult = <1>;
158 };
159
160 periph_clk: periph_clk {
161 #clock-cells = <0>;
162 compatible = "fixed-factor-clock";
163 clocks = <&a9pll>;
164 clock-div = <2>;
165 clock-mult = <1>;
166 };
167 };
168
169 axi: axi@18000000 {
170 compatible = "simple-bus";
171 ranges = <0x00000000 0x18000000 0x0011c40c>;
172 #address-cells = <1>;
173 #size-cells = <1>;
174
175 gpioa: gpio@20 {
176 compatible = "brcm,nsp-gpio-a";
177 reg = <0x0020 0x70>,
178 <0x3f1c4 0x1c>;
179 #gpio-cells = <2>;
180 gpio-controller;
181 ngpios = <32>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
185 gpio-ranges = <&pinctrl 0 0 32>;
186 };
187
188 uart0: serial@300 {
189 compatible = "ns16550a";
190 reg = <0x0300 0x100>;
191 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&osc>;
193 status = "disabled";
194 };
195
196 uart1: serial@400 {
197 compatible = "ns16550a";
198 reg = <0x0400 0x100>;
199 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&osc>;
201 status = "disabled";
202 };
203
204 dma: dma@20000 {
205 compatible = "arm,pl330", "arm,primecell";
206 reg = <0x20000 0x1000>;
207 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&iprocslow>;
217 clock-names = "apb_pclk";
218 #dma-cells = <1>;
219 dma-coherent;
220 status = "disabled";
221 };
222
223 sdio: mmc@21000 {
224 compatible = "brcm,sdhci-iproc-cygnus";
225 reg = <0x21000 0x100>;
226 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
227 sdhci,auto-cmd12;
228 clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
229 dma-coherent;
230 status = "disabled";
231 };
232
233 amac0: ethernet@22000 {
234 compatible = "brcm,nsp-amac";
235 reg = <0x022000 0x1000>,
236 <0x110000 0x1000>;
237 reg-names = "amac_base", "idm_base";
238 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
239 dma-coherent;
240 status = "disabled";
241 };
242
243 amac1: ethernet@23000 {
244 compatible = "brcm,nsp-amac";
245 reg = <0x023000 0x1000>,
246 <0x111000 0x1000>;
247 reg-names = "amac_base", "idm_base";
248 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
249 dma-coherent;
250 status = "disabled";
251 };
252
253 amac2: ethernet@24000 {
254 compatible = "brcm,nsp-amac";
255 reg = <0x024000 0x1000>,
256 <0x112000 0x1000>;
257 reg-names = "amac_base", "idm_base";
258 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
259 dma-coherent;
260 status = "disabled";
261 };
262
263 mailbox: mailbox@25c00 {
264 compatible = "brcm,iproc-fa2-mbox";
265 reg = <0x25c00 0x400>;
266 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
267 #mbox-cells = <1>;
268 brcm,rx-status-len = <32>;
269 brcm,use-bcm-hdr;
270 dma-coherent;
271 };
272
273 nand_controller: nand-controller@26000 {
274 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
275 reg = <0x026000 0x600>,
276 <0x11b408 0x600>,
277 <0x026f00 0x20>;
278 reg-names = "nand", "iproc-idm", "iproc-ext";
279 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
280
281 #address-cells = <1>;
282 #size-cells = <0>;
283
284 brcm,nand-has-wp;
285 };
286
287 qspi: spi@27200 {
288 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
289 reg = <0x027200 0x184>,
290 <0x027000 0x124>,
291 <0x11c408 0x004>,
292 <0x0273a0 0x01c>;
293 reg-names = "mspi", "bspi", "intr_regs",
294 "intr_status_reg";
295 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-names = "spi_lr_fullness_reached",
303 "spi_lr_session_aborted",
304 "spi_lr_impatient",
305 "spi_lr_session_done",
306 "spi_lr_overhead",
307 "mspi_done",
308 "mspi_halted";
309 clocks = <&iprocmed>;
310 clock-names = "iprocmed";
311 num-cs = <2>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 status = "disabled";
315 };
316
317 xhci: usb@29000 {
318 compatible = "generic-xhci";
319 reg = <0x29000 0x1000>;
320 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
321 phys = <&usb3_phy>;
322 phy-names = "usb3-phy";
323 dma-coherent;
324 status = "disabled";
325 };
326
327 ehci0: usb@2a000 {
328 compatible = "generic-ehci";
329 reg = <0x2a000 0x100>;
330 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
331 dma-coherent;
332 status = "disabled";
333 };
334
335 ohci0: usb@2b000 {
336 compatible = "generic-ohci";
337 reg = <0x2b000 0x100>;
338 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
339 dma-coherent;
340 status = "disabled";
341 };
342
343 crypto@2f000 {
344 compatible = "brcm,spum-nsp-crypto";
345 reg = <0x2f000 0x900>;
346 mboxes = <&mailbox 0>;
347 };
348
349 gpiob: gpio@30000 {
350 compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
351 reg = <0x30000 0x50>;
352 #gpio-cells = <2>;
353 gpio-controller;
354 ngpios = <4>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
358 };
359
360 pwm: pwm@31000 {
361 compatible = "brcm,iproc-pwm";
362 reg = <0x31000 0x28>;
363 clocks = <&osc>;
364 #pwm-cells = <3>;
365 status = "disabled";
366 };
367
368 mdio: mdio@32000 {
369 compatible = "brcm,iproc-mdio";
370 reg = <0x32000 0x8>;
371 #size-cells = <0>;
372 #address-cells = <1>;
373 };
374
375 mdio-mux@32000 {
376 compatible = "mdio-mux-mmioreg", "mdio-mux";
377 reg = <0x32000 0x4>;
378 mux-mask = <0x200>;
379 #address-cells = <1>;
380 #size-cells = <0>;
381 mdio-parent-bus = <&mdio>;
382
383 mdio_int: mdio@0 {
384 reg = <0x0>;
385 #address-cells = <1>;
386 #size-cells = <0>;
387
388 usb3_phy: usb3-phy@10 {
389 compatible = "brcm,ns-bx-usb3-phy";
390 reg = <0x10>;
391 usb3-dmp-syscon = <&usb3_dmp>;
392 #phy-cells = <0>;
393 status = "disabled";
394 };
395 };
396
397 mdio_ext: mdio@200 {
398 reg = <0x200>;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 };
402 };
403
404 rng: rng@33000 {
405 compatible = "brcm,bcm-nsp-rng";
406 reg = <0x33000 0x14>;
407 };
408
409 ccbtimer0: timer@34000 {
410 compatible = "arm,sp804", "arm,primecell";
411 reg = <0x34000 0x1000>;
412 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&iprocslow>;
415 clock-names = "apb_pclk";
416 };
417
418 ccbtimer1: timer@35000 {
419 compatible = "arm,sp804", "arm,primecell";
420 reg = <0x35000 0x1000>;
421 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&iprocslow>;
424 clock-names = "apb_pclk";
425 };
426
427 srab: ethernet-switch@36000 {
428 compatible = "brcm,nsp-srab";
429 reg = <0x36000 0x1000>,
430 <0x3f308 0x8>,
431 <0x3f410 0xc>;
432 reg-names = "srab", "mux_config", "sgmii_config";
433 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-names = "link_state_p0",
447 "link_state_p1",
448 "link_state_p2",
449 "link_state_p3",
450 "link_state_p4",
451 "link_state_p5",
452 "link_state_p7",
453 "link_state_p8",
454 "phy",
455 "ts",
456 "imp_sleep_timer_p5",
457 "imp_sleep_timer_p7",
458 "imp_sleep_timer_p8";
459 status = "disabled";
460
461 /* ports are defined in board DTS */
462 ports {
463 #address-cells = <1>;
464 #size-cells = <0>;
465 };
466 };
467
468 i2c0: i2c@38000 {
469 compatible = "brcm,iproc-i2c";
470 reg = <0x38000 0x50>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
474 clock-frequency = <100000>;
475 dma-coherent;
476 status = "disabled";
477 };
478
479 watchdog@39000 {
480 compatible = "arm,sp805", "arm,primecell";
481 reg = <0x39000 0x1000>;
482 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&iprocslow>, <&iprocslow>;
484 clock-names = "wdog_clk", "apb_pclk";
485 };
486
487 lcpll0: lcpll0@3f100 {
488 #clock-cells = <1>;
489 compatible = "brcm,nsp-lcpll0";
490 reg = <0x3f100 0x14>;
491 clocks = <&osc>;
492 clock-output-names = "lcpll0", "pcie_phy", "sdio",
493 "ddr_phy";
494 };
495
496 genpll: genpll@3f140 {
497 #clock-cells = <1>;
498 compatible = "brcm,nsp-genpll";
499 reg = <0x3f140 0x24>;
500 clocks = <&osc>;
501 clock-output-names = "genpll", "phy", "ethernetclk",
502 "usbclk", "iprocfast", "sata1",
503 "sata2";
504 };
505
506 pinctrl: pinctrl@3f1c0 {
507 compatible = "brcm,nsp-pinmux";
508 reg = <0x3f1c0 0x04>,
509 <0x30028 0x04>,
510 <0x3f408 0x04>;
511 };
512
513 thermal: thermal@3f2c0 {
514 compatible = "brcm,ns-thermal";
515 reg = <0x3f2c0 0x10>;
516 #thermal-sensor-cells = <0>;
517 };
518
519 sata_phy: sata_phy@40100 {
520 compatible = "brcm,iproc-nsp-sata-phy";
521 reg = <0x40100 0x340>;
522 reg-names = "phy";
523 #address-cells = <1>;
524 #size-cells = <0>;
525
526 sata_phy0: sata-phy@0 {
527 reg = <0>;
528 #phy-cells = <0>;
529 status = "disabled";
530 };
531
532 sata_phy1: sata-phy@1 {
533 reg = <1>;
534 #phy-cells = <0>;
535 status = "disabled";
536 };
537 };
538
539 sata: sata@41000 {
540 compatible = "brcm,bcm-nsp-ahci";
541 reg-names = "ahci", "top-ctrl";
542 reg = <0x41000 0x1000>, <0x40020 0x1c>;
543 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
544 #address-cells = <1>;
545 #size-cells = <0>;
546 dma-coherent;
547 status = "disabled";
548
549 sata0: sata-port@0 {
550 reg = <0>;
551 phys = <&sata_phy0>;
552 phy-names = "sata-phy";
553 };
554
555 sata1: sata-port@1 {
556 reg = <1>;
557 phys = <&sata_phy1>;
558 phy-names = "sata-phy";
559 };
560 };
561
562 usb3_dmp: syscon@104000 {
563 reg = <0x104000 0x1000>;
564 };
565 };
566
567 pcie0: pcie@18012000 {
568 compatible = "brcm,iproc-pcie";
569 reg = <0x18012000 0x1000>;
570
571 #interrupt-cells = <1>;
572 interrupt-map-mask = <0 0 0 0>;
573 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
574
575 linux,pci-domain = <0>;
576
577 bus-range = <0x00 0xff>;
578
579 #address-cells = <3>;
580 #size-cells = <2>;
581 device_type = "pci";
582
583 /* Note: The HW does not support I/O resources. So,
584 * only the memory resource range is being specified.
585 */
586 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
587
588 dma-coherent;
589 status = "disabled";
590
591 msi-parent = <&msi0>;
592 msi0: msi {
593 compatible = "brcm,iproc-msi";
594 msi-controller;
595 interrupt-parent = <&gic>;
596 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
600 brcm,pcie-msi-inten;
601 };
602 };
603
604 pcie1: pcie@18013000 {
605 compatible = "brcm,iproc-pcie";
606 reg = <0x18013000 0x1000>;
607
608 #interrupt-cells = <1>;
609 interrupt-map-mask = <0 0 0 0>;
610 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
611
612 linux,pci-domain = <1>;
613
614 bus-range = <0x00 0xff>;
615
616 #address-cells = <3>;
617 #size-cells = <2>;
618 device_type = "pci";
619
620 /* Note: The HW does not support I/O resources. So,
621 * only the memory resource range is being specified.
622 */
623 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
624
625 dma-coherent;
626 status = "disabled";
627
628 msi-parent = <&msi1>;
629 msi1: msi {
630 compatible = "brcm,iproc-msi";
631 msi-controller;
632 interrupt-parent = <&gic>;
633 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
637 brcm,pcie-msi-inten;
638 };
639 };
640
641 pcie2: pcie@18014000 {
642 compatible = "brcm,iproc-pcie";
643 reg = <0x18014000 0x1000>;
644
645 #interrupt-cells = <1>;
646 interrupt-map-mask = <0 0 0 0>;
647 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
648
649 linux,pci-domain = <2>;
650
651 bus-range = <0x00 0xff>;
652
653 #address-cells = <3>;
654 #size-cells = <2>;
655 device_type = "pci";
656
657 /* Note: The HW does not support I/O resources. So,
658 * only the memory resource range is being specified.
659 */
660 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
661
662 dma-coherent;
663 status = "disabled";
664
665 msi-parent = <&msi2>;
666 msi2: msi {
667 compatible = "brcm,iproc-msi";
668 msi-controller;
669 interrupt-parent = <&gic>;
670 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
674 brcm,pcie-msi-inten;
675 };
676 };
677
678 thermal-zones {
679 cpu-thermal {
680 polling-delay-passive = <0>;
681 polling-delay = <1000>;
682 coefficients = <(-556) 418000>;
683 thermal-sensors = <&thermal>;
684
685 trips {
686 cpu-crit {
687 temperature = <125000>;
688 hysteresis = <0>;
689 type = "critical";
690 };
691 };
692
693 cooling-maps {
694 };
695 };
696 };
697 };
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