1 // SPDX-License-Identifier: GPL-2.0
2 #include "bcm283x.dtsi"
3 #include "bcm2835-common.dtsi"
4
5 / {
6 compatible = "brcm,bcm2836";
7
8 soc {
9 ranges = <0x7e000000 0x3f000000 0x1000000>,
10 <0x40000000 0x40000000 0x00001000>;
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
15 reg = <0x40000000 0x100>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
19 };
20 };
21
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
24 interrupt-parent = <&local_intc>;
25 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
26 };
27
28 timer {
29 compatible = "arm,armv7-timer";
30 interrupt-parent = <&local_intc>;
31 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
32 <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
33 <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
34 <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
35 always-on;
36 };
37
38 cpus: cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41 enable-method = "brcm,bcm2836-smp";
42
43 /* Source for d/i-cache-line-size and d/i-cache-sets
44 * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System
45 * /About-the-L1-memory-system?lang=en
46 *
47 * Source for d/i-cache-size
48 * https://forums.raspberrypi.com/viewtopic.php?t=98428
49 */
50
51 v7_cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a7";
54 reg = <0xf00>;
55 clock-frequency = <800000000>;
56 d-cache-size = <0x8000>;
57 d-cache-line-size = <64>;
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
59 i-cache-size = <0x8000>;
60 i-cache-line-size = <32>;
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
62 next-level-cache = <&l2>;
63 };
64
65 v7_cpu1: cpu@1 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a7";
68 reg = <0xf01>;
69 clock-frequency = <800000000>;
70 d-cache-size = <0x8000>;
71 d-cache-line-size = <64>;
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
73 i-cache-size = <0x8000>;
74 i-cache-line-size = <32>;
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
76 next-level-cache = <&l2>;
77 };
78
79 v7_cpu2: cpu@2 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a7";
82 reg = <0xf02>;
83 clock-frequency = <800000000>;
84 d-cache-size = <0x8000>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
87 i-cache-size = <0x8000>;
88 i-cache-line-size = <32>;
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
90 next-level-cache = <&l2>;
91 };
92
93 v7_cpu3: cpu@3 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a7";
96 reg = <0xf03>;
97 clock-frequency = <800000000>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
101 i-cache-size = <0x8000>;
102 i-cache-line-size = <32>;
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
104 next-level-cache = <&l2>;
105 };
106
107 /* Source for cache-line-size + cache-sets
108 * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System
109 * /About-the-L2-Memory-system?lang=en
110 * Source for cache-size
111 * https://forums.raspberrypi.com/viewtopic.php?t=98428
112 */
113 l2: l2-cache0 {
114 compatible = "cache";
115 cache-unified;
116 cache-size = <0x80000>;
117 cache-line-size = <64>;
118 cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
119 cache-level = <2>;
120 };
121 };
122 };
123
124 /* Make the BCM2835-style global interrupt controller be a child of the
125 * CPU-local interrupt controller.
126 */
127 &intc {
128 compatible = "brcm,bcm2836-armctrl-ic";
129 reg = <0x7e00b200 0x200>;
130 interrupt-parent = <&local_intc>;
131 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
132 };
133
134 &cpu_thermal {
135 coefficients = <(-538) 407000>;
136 };
137
138 /* enable thermal sensor with the correct compatible property set */
139 &thermal {
140 compatible = "brcm,bcm2836-thermal";
141 status = "okay";
142 };
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