1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
7
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
9 * spinning.
10 */
11 /memreserve/ 0x00000000 0x00001000;
12
13 /* This include file covers the common peripherals and configuration between
14 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
15 * bcm2835.dtsi and bcm2836.dtsi.
16 */
17
18 / {
19 compatible = "brcm,bcm2835";
20 model = "BCM2835";
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 };
28
29 chosen {
30 stdout-path = "serial0:115200n8";
31 };
32
33 rmem: reserved-memory {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
37
38 cma: linux,cma {
39 compatible = "shared-dma-pool";
40 size = <0x4000000>; /* 64MB */
41 reusable;
42 linux,cma-default;
43 };
44 };
45
46 thermal-zones {
47 cpu_thermal: cpu-thermal {
48 polling-delay-passive = <0>;
49 polling-delay = <1000>;
50
51 trips {
52 cpu-crit {
53 temperature = <90000>;
54 hysteresis = <0>;
55 type = "critical";
56 };
57 };
58
59 cooling-maps {
60 };
61 };
62 };
63
64 soc {
65 compatible = "simple-bus";
66 #address-cells = <1>;
67 #size-cells = <1>;
68
69 system_timer: timer@7e003000 {
70 compatible = "brcm,bcm2835-system-timer";
71 reg = <0x7e003000 0x1000>;
72 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
73 /* This could be a reference to BCM2835_CLOCK_TIMER,
74 * but we don't have the driver using the common clock
75 * support yet.
76 */
77 clock-frequency = <1000000>;
78 };
79
80 txp: txp@7e004000 {
81 compatible = "brcm,bcm2835-txp";
82 reg = <0x7e004000 0x20>;
83 interrupts = <1 11>;
84 };
85
86 clocks: cprman@7e101000 {
87 compatible = "brcm,bcm2835-cprman";
88 #clock-cells = <1>;
89 reg = <0x7e101000 0x2000>;
90
91 /* CPRMAN derives almost everything from the
92 * platform's oscillator. However, the DSI
93 * pixel clocks come from the DSI analog PHY.
94 */
95 clocks = <&clk_osc>,
96 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
97 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
98 };
99
100 mailbox: mailbox@7e00b880 {
101 compatible = "brcm,bcm2835-mbox";
102 reg = <0x7e00b880 0x40>;
103 interrupts = <0 1>;
104 #mbox-cells = <0>;
105 };
106
107 gpio: gpio@7e200000 {
108 compatible = "brcm,bcm2835-gpio";
109 reg = <0x7e200000 0xb4>;
110 /*
111 * The GPIO IP block is designed for 3 banks of GPIOs.
112 * Each bank has a GPIO interrupt for itself.
113 * There is an overall "any bank" interrupt.
114 * In order, these are GIC interrupts 17, 18, 19, 20.
115 * Since the BCM2835 only has 2 banks, the 2nd bank
116 * interrupt output appears to be mirrored onto the
117 * 3rd bank's interrupt signal.
118 * So, a bank0 interrupt shows up on 17, 20, and
119 * a bank1 interrupt shows up on 18, 19, 20!
120 */
121 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
122
123 gpio-controller;
124 #gpio-cells = <2>;
125
126 interrupt-controller;
127 #interrupt-cells = <2>;
128
129 gpio-ranges = <&gpio 0 0 54>;
130
131 /* Defines common pin muxing groups
132 *
133 * While each pin can have its mux selected
134 * for various functions individually, some
135 * groups only make sense to switch to a
136 * particular function together.
137 */
138 dpi_gpio0: dpi-gpio0 {
139 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
140 12 13 14 15 16 17 18 19
141 20 21 22 23 24 25 26 27>;
142 brcm,function = <BCM2835_FSEL_ALT2>;
143 };
144 emmc_gpio22: emmc-gpio22 {
145 brcm,pins = <22 23 24 25 26 27>;
146 brcm,function = <BCM2835_FSEL_ALT3>;
147 };
148 emmc_gpio34: emmc-gpio34 {
149 brcm,pins = <34 35 36 37 38 39>;
150 brcm,function = <BCM2835_FSEL_ALT3>;
151 brcm,pull = <BCM2835_PUD_OFF
152 BCM2835_PUD_UP
153 BCM2835_PUD_UP
154 BCM2835_PUD_UP
155 BCM2835_PUD_UP
156 BCM2835_PUD_UP>;
157 };
158 emmc_gpio48: emmc-gpio48 {
159 brcm,pins = <48 49 50 51 52 53>;
160 brcm,function = <BCM2835_FSEL_ALT3>;
161 };
162
163 gpclk0_gpio4: gpclk0-gpio4 {
164 brcm,pins = <4>;
165 brcm,function = <BCM2835_FSEL_ALT0>;
166 };
167 gpclk1_gpio5: gpclk1-gpio5 {
168 brcm,pins = <5>;
169 brcm,function = <BCM2835_FSEL_ALT0>;
170 };
171 gpclk1_gpio42: gpclk1-gpio42 {
172 brcm,pins = <42>;
173 brcm,function = <BCM2835_FSEL_ALT0>;
174 };
175 gpclk1_gpio44: gpclk1-gpio44 {
176 brcm,pins = <44>;
177 brcm,function = <BCM2835_FSEL_ALT0>;
178 };
179 gpclk2_gpio6: gpclk2-gpio6 {
180 brcm,pins = <6>;
181 brcm,function = <BCM2835_FSEL_ALT0>;
182 };
183 gpclk2_gpio43: gpclk2-gpio43 {
184 brcm,pins = <43>;
185 brcm,function = <BCM2835_FSEL_ALT0>;
186 brcm,pull = <BCM2835_PUD_OFF>;
187 };
188
189 i2c0_gpio0: i2c0-gpio0 {
190 brcm,pins = <0 1>;
191 brcm,function = <BCM2835_FSEL_ALT0>;
192 };
193 i2c0_gpio28: i2c0-gpio28 {
194 brcm,pins = <28 29>;
195 brcm,function = <BCM2835_FSEL_ALT0>;
196 };
197 i2c0_gpio44: i2c0-gpio44 {
198 brcm,pins = <44 45>;
199 brcm,function = <BCM2835_FSEL_ALT1>;
200 };
201 i2c1_gpio2: i2c1-gpio2 {
202 brcm,pins = <2 3>;
203 brcm,function = <BCM2835_FSEL_ALT0>;
204 };
205 i2c1_gpio44: i2c1-gpio44 {
206 brcm,pins = <44 45>;
207 brcm,function = <BCM2835_FSEL_ALT2>;
208 };
209
210 jtag_gpio22: jtag-gpio22 {
211 brcm,pins = <22 23 24 25 26 27>;
212 brcm,function = <BCM2835_FSEL_ALT4>;
213 };
214
215 pcm_gpio18: pcm-gpio18 {
216 brcm,pins = <18 19 20 21>;
217 brcm,function = <BCM2835_FSEL_ALT0>;
218 };
219 pcm_gpio28: pcm-gpio28 {
220 brcm,pins = <28 29 30 31>;
221 brcm,function = <BCM2835_FSEL_ALT2>;
222 };
223
224 sdhost_gpio48: sdhost-gpio48 {
225 brcm,pins = <48 49 50 51 52 53>;
226 brcm,function = <BCM2835_FSEL_ALT0>;
227 };
228
229 spi0_gpio7: spi0-gpio7 {
230 brcm,pins = <7 8 9 10 11>;
231 brcm,function = <BCM2835_FSEL_ALT0>;
232 };
233 spi0_gpio35: spi0-gpio35 {
234 brcm,pins = <35 36 37 38 39>;
235 brcm,function = <BCM2835_FSEL_ALT0>;
236 };
237 spi1_gpio16: spi1-gpio16 {
238 brcm,pins = <16 17 18 19 20 21>;
239 brcm,function = <BCM2835_FSEL_ALT4>;
240 };
241 spi2_gpio40: spi2-gpio40 {
242 brcm,pins = <40 41 42 43 44 45>;
243 brcm,function = <BCM2835_FSEL_ALT4>;
244 };
245
246 uart0_gpio14: uart0-gpio14 {
247 brcm,pins = <14 15>;
248 brcm,function = <BCM2835_FSEL_ALT0>;
249 };
250 /* Separate from the uart0_gpio14 group
251 * because it conflicts with spi1_gpio16, and
252 * people often run uart0 on the two pins
253 * without flow control.
254 */
255 uart0_ctsrts_gpio16: uart0-ctsrts-gpio16 {
256 brcm,pins = <16 17>;
257 brcm,function = <BCM2835_FSEL_ALT3>;
258 };
259 uart0_ctsrts_gpio30: uart0-ctsrts-gpio30 {
260 brcm,pins = <30 31>;
261 brcm,function = <BCM2835_FSEL_ALT3>;
262 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
263 };
264 uart0_gpio32: uart0-gpio32 {
265 brcm,pins = <32 33>;
266 brcm,function = <BCM2835_FSEL_ALT3>;
267 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
268 };
269 uart0_gpio36: uart0-gpio36 {
270 brcm,pins = <36 37>;
271 brcm,function = <BCM2835_FSEL_ALT2>;
272 };
273 uart0_ctsrts_gpio38: uart0-ctsrts-gpio38 {
274 brcm,pins = <38 39>;
275 brcm,function = <BCM2835_FSEL_ALT2>;
276 };
277
278 uart1_gpio14: uart1-gpio14 {
279 brcm,pins = <14 15>;
280 brcm,function = <BCM2835_FSEL_ALT5>;
281 };
282 uart1_ctsrts_gpio16: uart1-ctsrts-gpio16 {
283 brcm,pins = <16 17>;
284 brcm,function = <BCM2835_FSEL_ALT5>;
285 };
286 uart1_gpio32: uart1-gpio32 {
287 brcm,pins = <32 33>;
288 brcm,function = <BCM2835_FSEL_ALT5>;
289 };
290 uart1_ctsrts_gpio30: uart1-ctsrts-gpio30 {
291 brcm,pins = <30 31>;
292 brcm,function = <BCM2835_FSEL_ALT5>;
293 };
294 uart1_gpio40: uart1-gpio40 {
295 brcm,pins = <40 41>;
296 brcm,function = <BCM2835_FSEL_ALT5>;
297 };
298 uart1_ctsrts_gpio42: uart1-ctsrts-gpio42 {
299 brcm,pins = <42 43>;
300 brcm,function = <BCM2835_FSEL_ALT5>;
301 };
302 };
303
304 uart0: serial@7e201000 {
305 compatible = "arm,pl011", "arm,primecell";
306 reg = <0x7e201000 0x200>;
307 interrupts = <2 25>;
308 clocks = <&clocks BCM2835_CLOCK_UART>,
309 <&clocks BCM2835_CLOCK_VPU>;
310 clock-names = "uartclk", "apb_pclk";
311 arm,primecell-periphid = <0x00241011>;
312 };
313
314 sdhost: mmc@7e202000 {
315 compatible = "brcm,bcm2835-sdhost";
316 reg = <0x7e202000 0x100>;
317 interrupts = <2 24>;
318 clocks = <&clocks BCM2835_CLOCK_VPU>;
319 status = "disabled";
320 };
321
322 i2s: i2s@7e203000 {
323 compatible = "brcm,bcm2835-i2s";
324 reg = <0x7e203000 0x24>;
325 clocks = <&clocks BCM2835_CLOCK_PCM>;
326 status = "disabled";
327 };
328
329 spi: spi@7e204000 {
330 compatible = "brcm,bcm2835-spi";
331 reg = <0x7e204000 0x200>;
332 interrupts = <2 22>;
333 clocks = <&clocks BCM2835_CLOCK_VPU>;
334 #address-cells = <1>;
335 #size-cells = <0>;
336 status = "disabled";
337 };
338
339 i2c0: i2c@7e205000 {
340 compatible = "brcm,bcm2835-i2c";
341 reg = <0x7e205000 0x200>;
342 interrupts = <2 21>;
343 clocks = <&clocks BCM2835_CLOCK_VPU>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 status = "disabled";
347 };
348
349 dpi: dpi@7e208000 {
350 compatible = "brcm,bcm2835-dpi";
351 reg = <0x7e208000 0x8c>;
352 clocks = <&clocks BCM2835_CLOCK_VPU>,
353 <&clocks BCM2835_CLOCK_DPI>;
354 clock-names = "core", "pixel";
355 status = "disabled";
356 };
357
358 dsi0: dsi@7e209000 {
359 compatible = "brcm,bcm2835-dsi0";
360 reg = <0x7e209000 0x78>;
361 interrupts = <2 4>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 #clock-cells = <1>;
365
366 clocks = <&clocks BCM2835_PLLA_DSI0>,
367 <&clocks BCM2835_CLOCK_DSI0E>,
368 <&clocks BCM2835_CLOCK_DSI0P>;
369 clock-names = "phy", "escape", "pixel";
370
371 clock-output-names = "dsi0_byte",
372 "dsi0_ddr2",
373 "dsi0_ddr";
374
375 status = "disabled";
376 };
377
378 aux: aux@7e215000 {
379 compatible = "brcm,bcm2835-aux";
380 #clock-cells = <1>;
381 reg = <0x7e215000 0x8>;
382 clocks = <&clocks BCM2835_CLOCK_VPU>;
383 };
384
385 uart1: serial@7e215040 {
386 compatible = "brcm,bcm2835-aux-uart";
387 reg = <0x7e215040 0x40>;
388 interrupts = <1 29>;
389 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
390 status = "disabled";
391 };
392
393 spi1: spi@7e215080 {
394 compatible = "brcm,bcm2835-aux-spi";
395 reg = <0x7e215080 0x40>;
396 interrupts = <1 29>;
397 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
398 #address-cells = <1>;
399 #size-cells = <0>;
400 status = "disabled";
401 };
402
403 spi2: spi@7e2150c0 {
404 compatible = "brcm,bcm2835-aux-spi";
405 reg = <0x7e2150c0 0x40>;
406 interrupts = <1 29>;
407 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 status = "disabled";
411 };
412
413 pwm: pwm@7e20c000 {
414 compatible = "brcm,bcm2835-pwm";
415 reg = <0x7e20c000 0x28>;
416 clocks = <&clocks BCM2835_CLOCK_PWM>;
417 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
418 assigned-clock-rates = <10000000>;
419 #pwm-cells = <3>;
420 status = "disabled";
421 };
422
423 sdhci: mmc@7e300000 {
424 compatible = "brcm,bcm2835-sdhci";
425 reg = <0x7e300000 0x100>;
426 interrupts = <2 30>;
427 clocks = <&clocks BCM2835_CLOCK_EMMC>;
428 status = "disabled";
429 };
430
431 hvs@7e400000 {
432 compatible = "brcm,bcm2835-hvs";
433 reg = <0x7e400000 0x6000>;
434 interrupts = <2 1>;
435 };
436
437 dsi1: dsi@7e700000 {
438 compatible = "brcm,bcm2835-dsi1";
439 reg = <0x7e700000 0x8c>;
440 interrupts = <2 12>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 #clock-cells = <1>;
444
445 clocks = <&clocks BCM2835_PLLD_DSI1>,
446 <&clocks BCM2835_CLOCK_DSI1E>,
447 <&clocks BCM2835_CLOCK_DSI1P>;
448 clock-names = "phy", "escape", "pixel";
449
450 clock-output-names = "dsi1_byte",
451 "dsi1_ddr2",
452 "dsi1_ddr";
453
454 status = "disabled";
455 };
456
457 csi0: csi@7e800000 {
458 compatible = "brcm,bcm2835-unicam";
459 reg = <0x7e800000 0x800>,
460 <0x7e802000 0x4>;
461 reg-names = "unicam", "cmi";
462 interrupts = <2 6>;
463 brcm,num-data-lanes = <2>;
464 status = "disabled";
465 port {
466 };
467 };
468
469 csi1: csi@7e801000 {
470 compatible = "brcm,bcm2835-unicam";
471 reg = <0x7e801000 0x800>,
472 <0x7e802004 0x4>;
473 reg-names = "unicam", "cmi";
474 interrupts = <2 7>;
475 brcm,num-data-lanes = <4>;
476 status = "disabled";
477 port {
478 };
479 };
480
481 i2c1: i2c@7e804000 {
482 compatible = "brcm,bcm2835-i2c";
483 reg = <0x7e804000 0x1000>;
484 interrupts = <2 21>;
485 clocks = <&clocks BCM2835_CLOCK_VPU>;
486 #address-cells = <1>;
487 #size-cells = <0>;
488 status = "disabled";
489 };
490
491 usb: usb@7e980000 {
492 compatible = "brcm,bcm2835-usb";
493 reg = <0x7e980000 0x10000>;
494 interrupts = <1 9>;
495 #address-cells = <1>;
496 #size-cells = <0>;
497 clocks = <&clk_usb>;
498 clock-names = "otg";
499 phys = <&usbphy>;
500 phy-names = "usb2-phy";
501 };
502 };
503
504 clocks {
505 /* The oscillator is the root of the clock tree. */
506 clk_osc: clk-osc {
507 compatible = "fixed-clock";
508 #clock-cells = <0>;
509 clock-output-names = "osc";
510 clock-frequency = <19200000>;
511 };
512
513 clk_usb: clk-usb {
514 compatible = "fixed-clock";
515 #clock-cells = <0>;
516 clock-output-names = "otg";
517 clock-frequency = <480000000>;
518 };
519 };
520
521 usbphy: phy {
522 compatible = "usb-nop-xceiv";
523 #phy-cells = <0>;
524 };
525 };
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