1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /*
3 * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
15
16 aliases {
17 serial0 = &uart0;
18 };
19
20 chosen {
21 stdout-path = "serial0:115200n8";
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a7";
31 reg = <0x0>;
32 };
33 };
34
35 mpcore@18310000 {
36 compatible = "simple-bus";
37 ranges = <0x00000000 0x18310000 0x00008000>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40
41 gic: interrupt-controller@1000 {
42 compatible = "arm,cortex-a7-gic";
43 #interrupt-cells = <3>;
44 #address-cells = <0>;
45 interrupt-controller;
46 reg = <0x1000 0x1000>,
47 <0x2000 0x0100>;
48 };
49 };
50
51 timer {
52 compatible = "arm,armv7-timer";
53 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
54 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
55 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
56 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
57 };
58
59 clocks {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges;
63
64 alp: oscillator {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <40000000>;
68 };
69 };
70
71 axi@18000000 {
72 compatible = "brcm,bus-axi";
73 reg = <0x18000000 0x1000>;
74 ranges = <0x00000000 0x18000000 0x00100000>;
75 #address-cells = <1>;
76 #size-cells = <1>;
77
78 #interrupt-cells = <1>;
79 interrupt-map-mask = <0x000fffff 0xffff>;
80 interrupt-map =
81 /* ChipCommon */
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
83
84 /* IEEE 802.11 0 */
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
86
87 /* PCIe Controller 0 */
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
92 <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
93 <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
94
95 /* USB 2.0 Controller */
96 <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
97
98 /* Ethernet Controller 0 */
99 <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
100
101 /* IEEE 802.11 1 */
102 <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
103
104 /* Ethernet Controller 1 */
105 <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
106
107 chipcommon: chipcommon@0 {
108 compatible = "simple-bus";
109 reg = <0x00000000 0x1000>;
110 ranges;
111
112 #address-cells = <1>;
113 #size-cells = <1>;
114
115 gpio-controller;
116 #gpio-cells = <2>;
117
118 uart0: serial@300 {
119 compatible = "ns16550a";
120 reg = <0x0300 0x100>;
121 interrupt-parent = <&gic>;
122 interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&alp>;
124 status = "okay";
125 };
126 };
127
128 pcie0: pcie@2000 {
129 reg = <0x00002000 0x1000>;
130
131 #address-cells = <3>;
132 #size-cells = <2>;
133 };
134
135 usb2: usb2@4000 {
136 reg = <0x4000 0x1000>;
137 ranges;
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 ehci: usb@4000 {
142 compatible = "generic-ehci";
143 reg = <0x4000 0x1000>;
144 interrupt-parent = <&gic>;
145 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
146
147 #address-cells = <1>;
148 #size-cells = <0>;
149
150 ehci_port1: port@1 {
151 reg = <1>;
152 #trigger-source-cells = <0>;
153 };
154
155 ehci_port2: port@2 {
156 reg = <2>;
157 #trigger-source-cells = <0>;
158 };
159 };
160
161 ohci: usb@d000 {
162 compatible = "generic-ohci";
163 reg = <0xd000 0x1000>;
164 interrupt-parent = <&gic>;
165 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
166
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 ohci_port1: port@1 {
171 reg = <1>;
172 #trigger-source-cells = <0>;
173 };
174
175 ohci_port2: port@2 {
176 reg = <2>;
177 #trigger-source-cells = <0>;
178 };
179 };
180 };
181
182 gmac0: ethernet@5000 {
183 reg = <0x5000 0x1000>;
184 phy-mode = "internal";
185
186 fixed-link {
187 speed = <1000>;
188 full-duplex;
189 };
190
191 mdio {
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 switch: switch@1e {
196 compatible = "brcm,bcm53125";
197 reg = <0x1e>;
198
199 status = "disabled";
200
201 ports {
202 #address-cells = <1>;
203 #size-cells = <0>;
204
205 port@0 {
206 reg = <0>;
207 };
208
209 port@1 {
210 reg = <1>;
211 };
212
213 port@2 {
214 reg = <2>;
215 };
216
217 port@3 {
218 reg = <3>;
219 };
220
221 port@4 {
222 reg = <4>;
223 };
224
225 port@5 {
226 reg = <5>;
227 ethernet = <&gmac1>;
228
229 fixed-link {
230 speed = <1000>;
231 full-duplex;
232 };
233 };
234
235 port@8 {
236 reg = <8>;
237 ethernet = <&gmac0>;
238 };
239 };
240 };
241 };
242 };
243
244 gmac1: ethernet@b000 {
245 reg = <0xb000 0x1000>;
246 phy-mode = "internal";
247
248 fixed-link {
249 speed = <1000>;
250 full-duplex;
251 };
252 };
253
254 pmu@12000 {
255 compatible = "simple-mfd", "syscon";
256 reg = <0x00012000 0x00001000>;
257
258 ilp: ilp {
259 compatible = "brcm,bcm53573-ilp";
260 clocks = <&alp>;
261 #clock-cells = <0>;
262 clock-output-names = "ilp";
263 };
264 };
265 };
266 };
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