1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8
9 / {
10 compatible = "brcm,bcm6855", "brcm,bcmbca";
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 interrupt-parent = <&gic>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 CA7_0: cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a7";
23 reg = <0x0>;
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
26 };
27
28 CA7_1: cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a7";
31 reg = <0x1>;
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
34 };
35
36 CA7_2: cpu@2 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a7";
39 reg = <0x2>;
40 next-level-cache = <&L2_0>;
41 enable-method = "psci";
42 };
43
44 L2_0: l2-cache0 {
45 compatible = "cache";
46 cache-level = <2>;
47 cache-unified;
48 };
49 };
50
51 timer {
52 compatible = "arm,armv7-timer";
53 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
54 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
55 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
56 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
57 arm,cpu-registers-not-fw-configured;
58 };
59
60 pmu: pmu {
61 compatible = "arm,cortex-a7-pmu";
62 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
65 interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
66 };
67
68 clocks: clocks {
69 periph_clk: periph-clk {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <200000000>;
73 };
74
75 uart_clk: uart-clk {
76 compatible = "fixed-factor-clock";
77 #clock-cells = <0>;
78 clocks = <&periph_clk>;
79 clock-div = <4>;
80 clock-mult = <1>;
81 };
82
83 hsspi_pll: hsspi-pll {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <200000000>;
87 };
88 };
89
90 psci {
91 compatible = "arm,psci-0.2";
92 method = "smc";
93 };
94
95 axi@81000000 {
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges = <0 0x81000000 0x8000>;
100
101 gic: interrupt-controller@1000 {
102 compatible = "arm,cortex-a7-gic";
103 #interrupt-cells = <3>;
104 interrupt-controller;
105 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
106 reg = <0x1000 0x1000>,
107 <0x2000 0x2000>,
108 <0x4000 0x2000>,
109 <0x6000 0x2000>;
110 };
111 };
112
113 bus@ff800000 {
114 compatible = "simple-bus";
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges = <0 0xff800000 0x800000>;
118
119 hsspi: spi@1000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1";
123 reg = <0x1000 0x600>, <0x2610 0x4>;
124 reg-names = "hsspi", "spim-ctrl";
125 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&hsspi_pll &hsspi_pll>;
127 clock-names = "hsspi", "pll";
128 num-cs = <8>;
129 status = "disabled";
130 };
131
132 nand_controller: nand-controller@1800 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
136 reg = <0x1800 0x600>, <0x2000 0x10>;
137 reg-names = "nand", "nand-int-base";
138 status = "disabled";
139
140 nandcs: nand@0 {
141 compatible = "brcm,nandcs";
142 reg = <0>;
143 };
144 };
145
146 uart0: serial@12000 {
147 compatible = "arm,pl011", "arm,primecell";
148 reg = <0x12000 0x1000>;
149 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&uart_clk>, <&uart_clk>;
151 clock-names = "uartclk", "apb_pclk";
152 status = "disabled";
153 };
154 };
155 };
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