1 // SPDX-License-Identifier: ISC
2 /*
3 * Device Tree file for the Goramo MultiLink Router
4 * There are two variants:
5 * - MultiLink Basic (a box)
6 * - MultiLink Max (19" rack mount)
7 * This device tree supports MultiLink Basic.
8 * This machine is based on IXP425.
9 * This is one of the few devices supporting the IXP4xx High-Speed Serial
10 * (HSS) link for a V.35 WAN interface.
11 * The hardware originates in Poland.
12 */
13
14 /dts-v1/;
15
16 #include "intel-ixp42x.dtsi"
17 #include <dt-bindings/input/input.h>
18
19 / {
20 model = "Goramo MultiLink Router";
21 compatible = "goramo,multilink-router", "intel,ixp42x";
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 memory@0 {
26 /*
27 * 64 MB of RAM according to the manual. The MultiLink
28 * Max has 128 MB.
29 */
30 device_type = "memory";
31 reg = <0x00000000 0x4000000>;
32 };
33
34 chosen {
35 bootargs = "console=ttyS0,115200n8";
36 stdout-path = "uart0:115200n8";
37 };
38
39 aliases {
40 serial0 = &uart0;
41 serial1 = &uart1;
42 };
43
44 /*
45 * 74HC4094 which is used as a rudimentary GPIO expander
46 * FIXME:
47 * - Create device tree bindings for this as GPIO expander
48 * - Write a pure DT GPIO driver using these bindings
49 * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
50 */
51 gpio_74: gpio-74hc4094 {
52 compatible = "nxp,74hc4094";
53 cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
54 d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
55 str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
56 /* oe-gpios is optional */
57 gpio-controller;
58 #gpio-cells = <2>;
59 /* We are not cascaded */
60 registers-number = <1>;
61 gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
62 "CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET",
63 "CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N";
64 };
65
66 soc {
67 bus@c4000000 {
68 flash@0,0 {
69 compatible = "intel,ixp4xx-flash", "cfi-flash";
70 bank-width = <2>;
71 /* Enable writes on the expansion bus */
72 intel,ixp4xx-eb-write-enable = <1>;
73 /* 16 MB of Flash mapped in at CS0 */
74 reg = <0 0x00000000 0x1000000>;
75
76 partitions {
77 compatible = "redboot-fis";
78 /* Eraseblock at 0x0fe0000 */
79 fis-index-block = <0x7f>;
80 };
81 };
82 };
83
84 pci@c0000000 {
85 status = "okay";
86
87 /*
88 * The device has 4 slots (IDSEL) with one dedicated IRQ per slot.
89 * The slots have Ethernet, Ethernet, NEC and MPCI.
90 * The IDSELs are 11, 12, 13, 14.
91 */
92 #interrupt-cells = <1>;
93 interrupt-map-mask = <0xf800 0 0 7>;
94 interrupt-map =
95 /* IDSEL 11 - Ethernet A */
96 <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
97 <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */
98 <0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */
99 <0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */
100 /* IDSEL 12 - Ethernet B */
101 <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
102 <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
103 <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
104 <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
105 /* IDSEL 13 - MPCI */
106 <0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */
107 <0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */
108 <0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */
109 <0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */
110 /* IDSEL 14 - NEC */
111 <0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */
112 <0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */
113 <0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */
114 <0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */
115 };
116
117 /* HSS links */
118 npe@c8006000 {
119 hss@0 {
120 status = "okay";
121 intel,queue-chl-rxtrig = <&qmgr 12>;
122 intel,queue-chl-txready = <&qmgr 34>;
123 intel,queue-pkt-rx = <&qmgr 13>;
124 intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
125 intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
126 intel,queue-pkt-txdone = <&qmgr 22>;
127 /* The Goramo GPIO-based clock etc control */
128 cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
129 rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
130 dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
131 dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
132 clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
133 };
134 hss@1 {
135 status = "okay";
136 intel,queue-chl-rxtrig = <&qmgr 10>;
137 intel,queue-chl-txready = <&qmgr 35>;
138 intel,queue-pkt-rx = <&qmgr 0>;
139 intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>;
140 intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>;
141 intel,queue-pkt-txdone = <&qmgr 9>;
142 /* The Goramo GPIO-based clock etc control */
143 cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
144 rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
145 dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
146 dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>;
147 clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>;
148 };
149 };
150
151 /* EthB */
152 ethernet@c8009000 {
153 status = "okay";
154 queue-rx = <&qmgr 3>;
155 queue-txready = <&qmgr 32>;
156 phy-mode = "rgmii";
157 phy-handle = <&phy0>;
158
159 mdio {
160 #address-cells = <1>;
161 #size-cells = <0>;
162
163 phy0: ethernet-phy@0 {
164 reg = <0>;
165 };
166
167 phy1: ethernet-phy@1 {
168 reg = <1>;
169 };
170 };
171 };
172
173 /* EthC */
174 ethernet@c800a000 {
175 status = "okay";
176 queue-rx = <&qmgr 4>;
177 queue-txready = <&qmgr 33>;
178 phy-mode = "rgmii";
179 phy-handle = <&phy1>;
180 };
181 };
182 };
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