1 // SPDX-License-Identifier: ISC
2 /*
3 * Device Tree file for the USRobotics USR8200 firewall
4 * VPN and NAS. Based on know-how from Peter Denison.
5 *
6 * This machine is based on IXP422, the USR internal codename
7 * is "Jeeves".
8 */
9
10 /dts-v1/;
11
12 #include "intel-ixp42x.dtsi"
13 #include <dt-bindings/input/input.h>
14
15 / {
16 model = "USRobotics USR8200";
17 compatible = "usr,usr8200", "intel,ixp42x";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 memory@0 {
22 device_type = "memory";
23 reg = <0x00000000 0x4000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyS0,115200n8";
28 stdout-path = "uart1:115200n8";
29 };
30
31 aliases {
32 /* These are switched around */
33 serial0 = &uart1;
34 serial1 = &uart0;
35 };
36
37 leds {
38 compatible = "gpio-leds";
39 ieee1394_led: led-1394 {
40 label = "usr8200:green:1394";
41 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
42 default-state = "off";
43 };
44 usb1_led: led-usb1 {
45 label = "usr8200:green:usb1";
46 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
47 default-state = "off";
48 };
49 usb2_led: led-usb2 {
50 label = "usr8200:green:usb2";
51 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
52 default-state = "off";
53 };
54 wireless_led: led-wireless {
55 /*
56 * This LED is mounted inside the case but cannot be
57 * seen from the outside: probably USR planned at one
58 * point for the device to have a wireless card, then
59 * changed their mind and didn't mount it, leaving the
60 * LED in place.
61 */
62 label = "usr8200:green:wireless";
63 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
64 default-state = "off";
65 };
66 pwr_led: led-pwr {
67 label = "usr8200:green:pwr";
68 gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
69 default-state = "on";
70 linux,default-trigger = "heartbeat";
71 };
72 };
73
74 gpio_keys {
75 compatible = "gpio-keys";
76
77 button-reset {
78 wakeup-source;
79 linux,code = <KEY_RESTART>;
80 label = "reset";
81 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
82 };
83 };
84
85 soc {
86 bus@c4000000 {
87 flash@0,0 {
88 compatible = "intel,ixp4xx-flash", "cfi-flash";
89 bank-width = <2>;
90 /* Enable writes on the expansion bus */
91 intel,ixp4xx-eb-write-enable = <1>;
92 /* 16 MB of Flash mapped in at CS0 */
93 reg = <0 0x00000000 0x1000000>;
94
95 partitions {
96 compatible = "redboot-fis";
97 /* Eraseblock at 0x0fe0000 */
98 fis-index-block = <0x7f>;
99 };
100 };
101 rtc@2,0 {
102 /* EPSON RTC7301 DG DIL-capsule */
103 compatible = "epson,rtc7301dg";
104 /*
105 * These timing settings were found in the boardfile patch:
106 * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
107 * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
108 */
109 intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
110 intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
111 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
112 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
113 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
114 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
115 intel,ixp4xx-eb-byte-access-on-halfword = <0>;
116 intel,ixp4xx-eb-mux-address-and-data = <0>;
117 intel,ixp4xx-eb-ahb-split-transfers = <0>;
118 intel,ixp4xx-eb-write-enable = <1>;
119 intel,ixp4xx-eb-byte-access = <1>;
120 /* 512 bytes at CS2 */
121 reg = <2 0x00000000 0x0000200>;
122 reg-io-width = <1>;
123 native-endian;
124 /* FIXME: try to check if there is an IRQ for the RTC? */
125 };
126 };
127
128 pci@c0000000 {
129 status = "okay";
130
131 /*
132 * Taken from USR8200 boardfile from OpenWrt
133 *
134 * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
135 * We assume the same IRQ for all pins on the remaining slots, that
136 * is what the boardfile was doing.
137 */
138 #interrupt-cells = <1>;
139 interrupt-map-mask = <0xf800 0 0 7>;
140 interrupt-map =
141 /* IDSEL 14 used for "Wireless" in the board file */
142 <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
143 /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
144 <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
145 /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
146 <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
147 <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
148 <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
149 };
150
151 gpio@c8004000 {
152 /* Enable clock out on GPIO 15 */
153 intel,ixp4xx-gpio15-clkout;
154 };
155
156 /* EthB WAN */
157 ethernet@c8009000 {
158 status = "okay";
159 queue-rx = <&qmgr 3>;
160 queue-txready = <&qmgr 20>;
161 phy-mode = "rgmii";
162 phy-handle = <&phy9>;
163
164 mdio {
165 #address-cells = <1>;
166 #size-cells = <0>;
167
168 /*
169 * PHY 0..4 are internal to the MV88E6060 switch but appear
170 * as independent devices.
171 */
172 phy0: ethernet-phy@0 {
173 reg = <0>;
174 };
175 phy1: ethernet-phy@1 {
176 reg = <1>;
177 };
178 phy2: ethernet-phy@2 {
179 reg = <2>;
180 };
181 phy3: ethernet-phy@3 {
182 reg = <3>;
183 };
184
185 /* Altima AMI101L used by the WAN port */
186 phy9: ethernet-phy@9 {
187 reg = <9>;
188 };
189
190 /* The switch uses MDIO addresses 16 thru 31 */
191 switch@16 {
192 compatible = "marvell,mv88e6060";
193 reg = <16>;
194
195 ports {
196 #address-cells = <1>;
197 #size-cells = <0>;
198
199 port@0 {
200 reg = <0>;
201 label = "lan1";
202 phy-handle = <&phy0>;
203 };
204
205 port@1 {
206 reg = <1>;
207 label = "lan2";
208 phy-handle = <&phy1>;
209 };
210
211 port@2 {
212 reg = <2>;
213 label = "lan3";
214 phy-handle = <&phy2>;
215 };
216
217 port@3 {
218 reg = <3>;
219 label = "lan4";
220 phy-handle = <&phy3>;
221 };
222
223 port@5 {
224 /* Port 5 is the CPU port according to the MV88E6060 datasheet */
225 reg = <5>;
226 phy-mode = "rgmii-id";
227 ethernet = <ðc>;
228 label = "cpu";
229 fixed-link {
230 speed = <100>;
231 full-duplex;
232 };
233 };
234 };
235 };
236 };
237 };
238
239 /* EthC LAN connected to the Marvell DSA Switch */
240 ethc: ethernet@c800a000 {
241 status = "okay";
242 queue-rx = <&qmgr 4>;
243 queue-txready = <&qmgr 21>;
244 phy-mode = "rgmii";
245 fixed-link {
246 speed = <100>;
247 full-duplex;
248 };
249 };
250 };
251 };
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