1 // SPDX-License-Identifier: ISC
2 /*
3 * Device Tree file for Gateworks IXP43x-based Cambria GW2358
4 */
5
6 /dts-v1/;
7
8 #include "intel-ixp43x.dtsi"
9
10 / {
11 model = "Gateworks Cambria GW2358";
12 compatible = "gateworks,gw2358", "intel,ixp43x";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 memory@0 {
17 /* 128 MB SDRAM */
18 device_type = "memory";
19 reg = <0x00000000 0x8000000>;
20 };
21
22 chosen {
23 bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
24 stdout-path = "uart0:115200n8";
25 };
26
27 aliases {
28 serial0 = &uart0;
29 };
30
31 leds {
32 compatible = "gpio-leds";
33 led-user {
34 label = "gw2358:green:LED";
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
36 default-state = "on";
37 linux,default-trigger = "heartbeat";
38 };
39 };
40
41
42 i2c {
43 compatible = "i2c-gpio";
44 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
45 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 hwmon@28 {
50 compatible = "adi,ad7418";
51 reg = <0x28>;
52 };
53 rtc: ds1672@68 {
54 compatible = "dallas,ds1672";
55 reg = <0x68>;
56 };
57 eeprom@51 {
58 compatible = "atmel,24c08";
59 reg = <0x51>;
60 pagesize = <16>;
61 size = <1024>;
62 read-only;
63 };
64 pld0: pld@56 {
65 compatible = "gateworks,pld-gpio";
66 reg = <0x56>;
67 gpio-controller;
68 #gpio-cells = <2>;
69 };
70 /* This PLD just handles the LED and user button */
71 pld1: pld@57 {
72 compatible = "gateworks,pld-gpio";
73 reg = <0x57>;
74 gpio-controller;
75 #gpio-cells = <2>;
76 };
77 };
78
79 soc {
80 bus@c4000000 {
81 flash@0,0 {
82 compatible = "intel,ixp4xx-flash", "cfi-flash";
83 bank-width = <2>;
84 /* Enable writes on the expansion bus */
85 intel,ixp4xx-eb-write-enable = <1>;
86 /*
87 * 32 MB of Flash in 0x20000 byte blocks
88 * mapped in at CS0 and CS1
89 */
90 reg = <0 0x00000000 0x2000000>;
91
92 partitions {
93 compatible = "redboot-fis";
94 /* Eraseblock at 0x1fe0000 */
95 fis-index-block = <0xff>;
96 };
97 };
98 ide@3,0 {
99 compatible = "intel,ixp4xx-compact-flash";
100 /*
101 * Set up expansion bus config to a really slow timing.
102 * The CF driver will dynamically reconfigure these timings
103 * depending on selected PIO mode (0-4).
104 */
105 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
106 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
107 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
108 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
109 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
110 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
111 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
112 intel,ixp4xx-eb-mux-address-and-data = <0>;
113 intel,ixp4xx-eb-ahb-split-transfers = <0>;
114 intel,ixp4xx-eb-write-enable = <1>;
115 intel,ixp4xx-eb-byte-access = <1>;
116 /* First register set is CMD second is CTL */
117 reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>;
118 interrupt-parent = <&gpio0>;
119 interrupts = <12 IRQ_TYPE_EDGE_RISING>;
120 };
121 };
122
123 pci@c0000000 {
124 status = "okay";
125
126 /*
127 * In the boardfile for the Cambria from OpenWRT the interrupts
128 * are assigned one per IDSEL, so all 4 interrupts from IDSEL
129 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
130 * connected to IRQ 10 etc. I find this highly unlikely so I
131 * have instead assumed that they are rotated (swizzled) like
132 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
133 */
134 #interrupt-cells = <1>;
135 interrupt-map-mask = <0xf800 0 0 7>;
136 interrupt-map =
137 /* IDSEL 1 */
138 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
139 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
140 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
141 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
142 /* IDSEL 2 */
143 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
144 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
145 <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
146 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
147 /* IDSEL 3 */
148 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
149 <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
150 <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
151 <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
152 /* IDSEL 4 */
153 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
154 <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
155 <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
156 <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
157 /* IDSEL 6 */
158 <0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
159 <0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
160 <0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */
161 <0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
162 /* IDSEL 15 */
163 <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
164 <0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
165 <0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
166 <0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
167 };
168
169 ethernet@c800a000 {
170 status = "okay";
171 queue-rx = <&qmgr 4>;
172 queue-txready = <&qmgr 21>;
173 phy-mode = "rgmii";
174 phy-handle = <&phy1>;
175
176 mdio {
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 phy1: ethernet-phy@1 {
181 reg = <1>;
182 };
183
184 phy2: ethernet-phy@2 {
185 reg = <2>;
186 };
187 };
188 };
189
190 ethernet@c800c000 {
191 status = "okay";
192 queue-rx = <&qmgr 2>;
193 queue-txready = <&qmgr 19>;
194 phy-mode = "rgmii";
195 phy-handle = <&phy2>;
196 intel,npe-handle = <&npe 0>;
197 };
198 };
199 };
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