1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */
3
4 /dts-v1/;
5 #include "armada-385.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8
9 / {
10 model = "Netgear GS110EMX";
11 compatible = "netgear,gs110emx", "marvell,armada380";
12
13 aliases {
14 /* So that mvebu u-boot can update the MAC addresses */
15 ethernet1 = ð0;
16 };
17
18 chosen {
19 stdout-path = "serial0:115200n8";
20 };
21
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-0 = <&front_button_pins>;
25 pinctrl-names = "default";
26
27 key-factory-default {
28 label = "Factory Default";
29 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
30 linux,code = <KEY_RESTART>;
31 };
32 };
33
34 memory {
35 device_type = "memory";
36 reg = <0x00000000 0x08000000>; /* 128 MB */
37 };
38
39 soc {
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
45
46 internal-regs {
47 rtc@a3800 {
48 /*
49 * If the rtc doesn't work, run "date reset"
50 * twice in u-boot.
51 */
52 status = "okay";
53 };
54 };
55 };
56 };
57
58 ð0 {
59 /* ethernet@70000 */
60 bm,pool-long = <0>;
61 bm,pool-short = <1>;
62 buffer-manager = <&bm>;
63 phy-mode = "rgmii-id";
64 pinctrl-0 = <&ge0_rgmii_pins>;
65 pinctrl-names = "default";
66 status = "okay";
67
68 fixed-link {
69 full-duplex;
70 pause;
71 speed = <1000>;
72 };
73 };
74
75 &mdio {
76 pinctrl-names = "default";
77 pinctrl-0 = <&mdio_pins>;
78 status = "okay";
79
80 ethernet-switch@0 {
81 compatible = "marvell,mv88e6190";
82 #interrupt-cells = <2>;
83 interrupt-controller;
84 interrupt-parent = <&gpio1>;
85 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
86 pinctrl-0 = <&switch_interrupt_pins>;
87 pinctrl-names = "default";
88 reg = <0>;
89
90 mdio {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 switch0phy1: ethernet-phy@1 {
95 reg = <0x1>;
96 };
97
98 switch0phy2: ethernet-phy@2 {
99 reg = <0x2>;
100 };
101
102 switch0phy3: ethernet-phy@3 {
103 reg = <0x3>;
104 };
105
106 switch0phy4: ethernet-phy@4 {
107 reg = <0x4>;
108 };
109
110 switch0phy5: ethernet-phy@5 {
111 reg = <0x5>;
112 };
113
114 switch0phy6: ethernet-phy@6 {
115 reg = <0x6>;
116 };
117
118 switch0phy7: ethernet-phy@7 {
119 reg = <0x7>;
120 };
121
122 switch0phy8: ethernet-phy@8 {
123 reg = <0x8>;
124 };
125 };
126
127 mdio-external {
128 compatible = "marvell,mv88e6xxx-mdio-external";
129 #address-cells = <1>;
130 #size-cells = <0>;
131
132 phy1: ethernet-phy@b {
133 reg = <0xb>;
134 compatible = "ethernet-phy-ieee802.3-c45";
135 };
136
137 phy2: ethernet-phy@c {
138 reg = <0xc>;
139 compatible = "ethernet-phy-ieee802.3-c45";
140 };
141 };
142
143 ethernet-ports {
144 #address-cells = <1>;
145 #size-cells = <0>;
146
147 ethernet-port@0 {
148 ethernet = <ð0>;
149 phy-mode = "rgmii";
150 reg = <0>;
151
152 fixed-link {
153 full-duplex;
154 pause;
155 speed = <1000>;
156 };
157 };
158
159 ethernet-port@1 {
160 label = "lan1";
161 phy-handle = <&switch0phy1>;
162 reg = <1>;
163 };
164
165 ethernet-port@2 {
166 label = "lan2";
167 phy-handle = <&switch0phy2>;
168 reg = <2>;
169 };
170
171 ethernet-port@3 {
172 label = "lan3";
173 phy-handle = <&switch0phy3>;
174 reg = <3>;
175 };
176
177 ethernet-port@4 {
178 label = "lan4";
179 phy-handle = <&switch0phy4>;
180 reg = <4>;
181 };
182
183 ethernet-port@5 {
184 label = "lan5";
185 phy-handle = <&switch0phy5>;
186 reg = <5>;
187 };
188
189 ethernet-port@6 {
190 label = "lan6";
191 phy-handle = <&switch0phy6>;
192 reg = <6>;
193 };
194
195 ethernet-port@7 {
196 label = "lan7";
197 phy-handle = <&switch0phy7>;
198 reg = <7>;
199 };
200
201 ethernet-port@8 {
202 label = "lan8";
203 phy-handle = <&switch0phy8>;
204 reg = <8>;
205 };
206
207 ethernet-port@9 {
208 /* 88X3310P external phy */
209 label = "lan9";
210 phy-handle = <&phy1>;
211 phy-mode = "xaui";
212 reg = <9>;
213 };
214
215 ethernet-port@a {
216 /* 88X3310P external phy */
217 label = "lan10";
218 phy-handle = <&phy2>;
219 phy-mode = "xaui";
220 reg = <0xa>;
221 };
222 };
223 };
224 };
225
226 &pinctrl {
227 front_button_pins: front-button-pins {
228 marvell,pins = "mpp38";
229 marvell,function = "gpio";
230 };
231
232 switch_interrupt_pins: switch-interrupt-pins {
233 marvell,pins = "mpp39";
234 marvell,function = "gpio";
235 };
236 };
237
238 &spi0 {
239 pinctrl-0 = <&spi0_pins>;
240 pinctrl-names = "default";
241 status = "okay";
242
243 flash@0 {
244 #address-cells = <1>;
245 #size-cells = <1>;
246 compatible = "jedec,spi-nor";
247 reg = <0>; /* Chip select 0 */
248 spi-max-frequency = <3000000>;
249
250 partitions {
251 compatible = "fixed-partitions";
252 #address-cells = <1>;
253 #size-cells = <1>;
254
255 partition@0 {
256 label = "boot";
257 read-only;
258 reg = <0x00000000 0x00100000>;
259 };
260
261 partition@100000 {
262 label = "env";
263 reg = <0x00100000 0x00010000>;
264 };
265
266 partition@200000 {
267 label = "rsv";
268 reg = <0x00110000 0x00010000>;
269 };
270
271 partition@300000 {
272 label = "image0";
273 reg = <0x00120000 0x00900000>;
274 };
275
276 partition@400000 {
277 label = "config";
278 reg = <0x00a20000 0x00300000>;
279 };
280
281 partition@480000 {
282 label = "debug";
283 reg = <0x00d20000 0x002e0000>;
284 };
285 };
286 };
287 };
288
289 &uart0 {
290 pinctrl-0 = <&uart0_pins>;
291 pinctrl-names = "default";
292 status = "okay";
293 };
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