1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Device Tree file for the Turris Omnia
4 *
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
7 *
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
9 */
10
11 /dts-v1/;
12
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/leds/common.h>
16 #include "armada-385.dtsi"
17
18 / {
19 model = "Turris Omnia";
20 compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
21
22 chosen {
23 stdout-path = &uart0;
24 };
25
26 aliases {
27 ethernet0 = ð0;
28 ethernet1 = ð1;
29 ethernet2 = ð2;
30 };
31
32 memory {
33 device_type = "memory";
34 reg = <0x00000000 0x40000000>; /* 1024 MB */
35 };
36
37 soc {
38 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
39 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
40 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
41 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
42 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
43
44 internal-regs {
45
46 /* USB part of the PCIe2/USB 2.0 port */
47 usb@58000 {
48 status = "okay";
49 };
50
51 sata@a8000 {
52 status = "okay";
53 };
54
55 sdhci@d8000 {
56 pinctrl-names = "default";
57 pinctrl-0 = <&sdhci_pins>;
58 status = "okay";
59
60 bus-width = <8>;
61 no-1-8-v;
62 non-removable;
63 };
64
65 usb3@f0000 {
66 status = "okay";
67 };
68
69 usb3@f8000 {
70 status = "okay";
71 };
72 };
73
74 pcie {
75 status = "okay";
76
77 pcie@1,0 {
78 /* Port 0, Lane 0 */
79 status = "okay";
80 slot-power-limit-milliwatt = <10000>;
81 };
82
83 pcie@2,0 {
84 /* Port 1, Lane 0 */
85 status = "okay";
86 slot-power-limit-milliwatt = <10000>;
87 };
88
89 pcie@3,0 {
90 /* Port 2, Lane 0 */
91 status = "okay";
92 slot-power-limit-milliwatt = <10000>;
93 };
94 };
95 };
96
97 sfp: sfp {
98 compatible = "sff,sfp";
99 i2c-bus = <&sfp_i2c>;
100 tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
101 tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
102 rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
103 los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
104 mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
105 maximum-power-milliwatt = <3000>;
106
107 /*
108 * For now this has to be enabled at boot time by U-Boot when
109 * a SFP module is present. Read more in the comment in the
110 * eth2 node below.
111 */
112 status = "disabled";
113 };
114
115 gpio-keys {
116 compatible = "gpio-keys";
117
118 front-button {
119 label = "Front Button";
120 linux,code = <KEY_VENDOR>;
121 linux,can-disable;
122 gpios = <&mcu 0 12 GPIO_ACTIVE_HIGH>;
123 /* debouncing is done by the microcontroller */
124 debounce-interval = <0>;
125 };
126 };
127
128 sound {
129 compatible = "simple-audio-card";
130 simple-audio-card,name = "SPDIF";
131 simple-audio-card,format = "i2s";
132
133 simple-audio-card,cpu {
134 sound-dai = <&audio_controller 1>;
135 };
136
137 simple-audio-card,codec {
138 sound-dai = <&spdif_out>;
139 };
140 };
141
142 spdif_out: spdif-out {
143 #sound-dai-cells = <0>;
144 compatible = "linux,spdif-dit";
145 };
146 };
147
148 &audio_controller {
149 /* Pin header U16, GPIO51 in SPDIFO mode */
150 pinctrl-0 = <&spdif_pins>;
151 pinctrl-names = "default";
152 spdif-mode;
153 status = "okay";
154 };
155
156 &bm {
157 status = "okay";
158 };
159
160 &bm_bppi {
161 status = "okay";
162 };
163
164 /* Connected to 88E6176 switch, port 6 */
165 ð0 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&ge0_rgmii_pins>;
168 status = "okay";
169 phy-mode = "rgmii";
170 buffer-manager = <&bm>;
171 bm,pool-long = <0>;
172 bm,pool-short = <3>;
173
174 fixed-link {
175 speed = <1000>;
176 full-duplex;
177 };
178 };
179
180 /* Connected to 88E6176 switch, port 5 */
181 ð1 {
182 pinctrl-names = "default";
183 pinctrl-0 = <&ge1_rgmii_pins>;
184 status = "okay";
185 phy-mode = "rgmii";
186 buffer-manager = <&bm>;
187 bm,pool-long = <1>;
188 bm,pool-short = <3>;
189
190 fixed-link {
191 speed = <1000>;
192 full-duplex;
193 };
194 };
195
196 /* WAN port */
197 ð2 {
198 /*
199 * eth2 is connected via a multiplexor to both the SFP cage and to
200 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
201 * a SFP module is present, as determined by the mode-def0 GPIO.
202 *
203 * Until kernel supports this configuration properly, in case SFP module
204 * is present, U-Boot has to enable the sfp node above, remove phy
205 * handle and add managed = "in-band-status" property.
206 */
207 status = "okay";
208 phy-mode = "sgmii";
209 phy-handle = <&phy1>;
210 phys = <&comphy5 2>;
211 sfp = <&sfp>;
212 buffer-manager = <&bm>;
213 bm,pool-long = <2>;
214 bm,pool-short = <3>;
215 label = "wan";
216 };
217
218 &i2c0 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c0_pins>;
221 status = "okay";
222
223 i2cmux@70 {
224 compatible = "nxp,pca9547";
225 #address-cells = <1>;
226 #size-cells = <0>;
227 reg = <0x70>;
228
229 i2c@0 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 reg = <0>;
233
234 mcu: system-controller@2a {
235 compatible = "cznic,turris-omnia-mcu";
236 reg = <0x2a>;
237
238 pinctrl-names = "default";
239 pinctrl-0 = <&mcu_pins>;
240
241 interrupt-parent = <&gpio1>;
242 interrupts = <11 IRQ_TYPE_NONE>;
243
244 gpio-controller;
245 #gpio-cells = <3>;
246
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 };
250
251 led-controller@2b {
252 compatible = "cznic,turris-omnia-leds";
253 reg = <0x2b>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 status = "okay";
257
258 /*
259 * LEDs are controlled by MCU (STM32F0) at
260 * address 0x2b.
261 *
262 * LED functions are not stable yet:
263 * - there are 3 LEDs connected via MCU to PCIe
264 * ports. One of these ports supports mSATA.
265 * There is no mSATA nor PCIe function.
266 * For now we use LED_FUNCTION_WLAN, since
267 * in most cases users have wifi cards in
268 * these slots
269 * - there are 2 LEDs dedicated for user: A and
270 * B. Again there is no such function defined.
271 * For now we use LED_FUNCTION_INDICATOR
272 */
273
274 multi-led@0 {
275 reg = <0x0>;
276 color = <LED_COLOR_ID_RGB>;
277 function = LED_FUNCTION_INDICATOR;
278 function-enumerator = <2>;
279 };
280
281 multi-led@1 {
282 reg = <0x1>;
283 color = <LED_COLOR_ID_RGB>;
284 function = LED_FUNCTION_INDICATOR;
285 function-enumerator = <1>;
286 };
287
288 multi-led@2 {
289 reg = <0x2>;
290 color = <LED_COLOR_ID_RGB>;
291 function = LED_FUNCTION_WLAN;
292 function-enumerator = <3>;
293 };
294
295 multi-led@3 {
296 reg = <0x3>;
297 color = <LED_COLOR_ID_RGB>;
298 function = LED_FUNCTION_WLAN;
299 function-enumerator = <2>;
300 };
301
302 multi-led@4 {
303 reg = <0x4>;
304 color = <LED_COLOR_ID_RGB>;
305 function = LED_FUNCTION_WLAN;
306 function-enumerator = <1>;
307 };
308
309 multi-led@5 {
310 reg = <0x5>;
311 color = <LED_COLOR_ID_RGB>;
312 function = LED_FUNCTION_WAN;
313 };
314
315 multi-led@6 {
316 reg = <0x6>;
317 color = <LED_COLOR_ID_RGB>;
318 function = LED_FUNCTION_LAN;
319 function-enumerator = <4>;
320 };
321
322 multi-led@7 {
323 reg = <0x7>;
324 color = <LED_COLOR_ID_RGB>;
325 function = LED_FUNCTION_LAN;
326 function-enumerator = <3>;
327 };
328
329 multi-led@8 {
330 reg = <0x8>;
331 color = <LED_COLOR_ID_RGB>;
332 function = LED_FUNCTION_LAN;
333 function-enumerator = <2>;
334 };
335
336 multi-led@9 {
337 reg = <0x9>;
338 color = <LED_COLOR_ID_RGB>;
339 function = LED_FUNCTION_LAN;
340 function-enumerator = <1>;
341 };
342
343 multi-led@a {
344 reg = <0xa>;
345 color = <LED_COLOR_ID_RGB>;
346 function = LED_FUNCTION_LAN;
347 function-enumerator = <0>;
348 };
349
350 multi-led@b {
351 reg = <0xb>;
352 color = <LED_COLOR_ID_RGB>;
353 function = LED_FUNCTION_POWER;
354 };
355 };
356
357 eeprom@54 {
358 compatible = "atmel,24c64";
359 reg = <0x54>;
360
361 /* The EEPROM contains data for bootloader.
362 * Contents:
363 * struct omnia_eeprom {
364 * u32 magic; (=0x0341a034 in LE)
365 * u32 ramsize; (in GiB)
366 * char regdomain[4];
367 * u32 crc32;
368 * };
369 */
370 };
371 };
372
373 i2c@1 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 reg = <1>;
377
378 /* routed to PCIe0/mSATA connector (CN7A) */
379 };
380
381 i2c@2 {
382 #address-cells = <1>;
383 #size-cells = <0>;
384 reg = <2>;
385
386 /* routed to PCIe1/USB2 connector (CN61A) */
387 };
388
389 i2c@3 {
390 #address-cells = <1>;
391 #size-cells = <0>;
392 reg = <3>;
393
394 /* routed to PCIe2 connector (CN62A) */
395 };
396
397 sfp_i2c: i2c@4 {
398 #address-cells = <1>;
399 #size-cells = <0>;
400 reg = <4>;
401
402 /* routed to SFP+ */
403 };
404
405 i2c@5 {
406 #address-cells = <1>;
407 #size-cells = <0>;
408 reg = <5>;
409
410 /* ATSHA204A-MAHDA-T crypto module */
411 crypto@64 {
412 compatible = "atmel,atsha204a";
413 reg = <0x64>;
414 };
415 };
416
417 i2c@6 {
418 #address-cells = <1>;
419 #size-cells = <0>;
420 reg = <6>;
421
422 /* exposed on pin header */
423 };
424
425 i2c@7 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 reg = <7>;
429
430 pcawan: gpio@71 {
431 /*
432 * GPIO expander for SFP+ signals and
433 * and phy irq
434 */
435 compatible = "nxp,pca9538";
436 reg = <0x71>;
437
438 pinctrl-names = "default";
439 pinctrl-0 = <&pcawan_pins>;
440
441 interrupt-parent = <&gpio1>;
442 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
443
444 gpio-controller;
445 #gpio-cells = <2>;
446 };
447 };
448 };
449 };
450
451 &mdio {
452 pinctrl-names = "default";
453 pinctrl-0 = <&mdio_pins>;
454 status = "okay";
455
456 phy1: ethernet-phy@1 {
457 compatible = "ethernet-phy-ieee802.3-c22";
458 reg = <1>;
459 marvell,reg-init = <3 18 0 0x4985>,
460 <3 16 0xfff0 0x0001>;
461
462 /* irq is connected to &pcawan pin 7 */
463 };
464
465 /* Switch MV88E6176 at address 0x10 */
466 ethernet-switch@10 {
467 pinctrl-names = "default";
468 pinctrl-0 = <&swint_pins>;
469 compatible = "marvell,mv88e6085";
470
471 dsa,member = <0 0>;
472 reg = <0x10>;
473
474 interrupt-parent = <&gpio1>;
475 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
476
477 ethernet-ports {
478 #address-cells = <1>;
479 #size-cells = <0>;
480
481 ethernet-port@0 {
482 reg = <0>;
483 label = "lan0";
484 };
485
486 ethernet-port@1 {
487 reg = <1>;
488 label = "lan1";
489 };
490
491 ethernet-port@2 {
492 reg = <2>;
493 label = "lan2";
494 };
495
496 ethernet-port@3 {
497 reg = <3>;
498 label = "lan3";
499 };
500
501 ethernet-port@4 {
502 reg = <4>;
503 label = "lan4";
504 };
505
506 ethernet-port@5 {
507 reg = <5>;
508 ethernet = <ð1>;
509 phy-mode = "rgmii-id";
510
511 fixed-link {
512 speed = <1000>;
513 full-duplex;
514 };
515 };
516
517 ethernet-port@6 {
518 reg = <6>;
519 ethernet = <ð0>;
520 phy-mode = "rgmii-id";
521
522 fixed-link {
523 speed = <1000>;
524 full-duplex;
525 };
526 };
527 };
528 };
529 };
530
531 &pinctrl {
532 mcu_pins: mcu-pins {
533 marvell,pins = "mpp43";
534 marvell,function = "gpio";
535 };
536
537 pcawan_pins: pcawan-pins {
538 marvell,pins = "mpp46";
539 marvell,function = "gpio";
540 };
541
542 swint_pins: swint-pins {
543 marvell,pins = "mpp45";
544 marvell,function = "gpio";
545 };
546
547 spi0cs0_pins: spi0cs0-pins {
548 marvell,pins = "mpp25";
549 marvell,function = "spi0";
550 };
551
552 spi0cs2_pins: spi0cs2-pins {
553 marvell,pins = "mpp26";
554 marvell,function = "spi0";
555 };
556 };
557
558 &spi0 {
559 pinctrl-names = "default";
560 pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
561 status = "okay";
562
563 flash@0 {
564 compatible = "spansion,s25fl164k", "jedec,spi-nor";
565 #address-cells = <1>;
566 #size-cells = <1>;
567 reg = <0>;
568 spi-max-frequency = <40000000>;
569
570 partitions {
571 compatible = "fixed-partitions";
572 #address-cells = <1>;
573 #size-cells = <1>;
574
575 partition@0 {
576 reg = <0x0 0x00100000>;
577 label = "U-Boot";
578 };
579
580 partition@100000 {
581 reg = <0x00100000 0x00700000>;
582 label = "Rescue system";
583 };
584 };
585 };
586
587 /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
588 };
589
590 &uart0 {
591 /* Pin header CN10 */
592 pinctrl-names = "default";
593 pinctrl-0 = <&uart0_pins>;
594 status = "okay";
595 };
596
597 &uart1 {
598 /* Pin header CN11 */
599 pinctrl-names = "default";
600 pinctrl-0 = <&uart1_pins>;
601 status = "okay";
602 };
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