1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada XP family SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * Contains definitions specific to the Armada XP MV78230 SoC that are not
10 * common to all Armada XP SoCs.
11 */
12
13 #include "armada-xp.dtsi"
14
15 / {
16 model = "Marvell Armada XP MV78230 SoC";
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
18
19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "marvell,sheeva-v7";
32 reg = <0>;
33 clocks = <&cpuclk 0>;
34 clock-latency = <1000000>;
35 };
36
37 cpu@1 {
38 device_type = "cpu";
39 compatible = "marvell,sheeva-v7";
40 reg = <1>;
41 clocks = <&cpuclk 1>;
42 clock-latency = <1000000>;
43 };
44 };
45
46 soc {
47 /*
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is
50 * x1 only.
51 */
52 pciec: pcie@82000000 {
53 compatible = "marvell,armada-xp-pcie";
54 status = "disabled";
55 device_type = "pci";
56
57 #address-cells = <3>;
58 #size-cells = <2>;
59
60 msi-parent = <&mpic>;
61 bus-range = <0x00 0xff>;
62
63 ranges =
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
73 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
74 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
75 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
76 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
77 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
78 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
79
80 pcie1: pcie@1,0 {
81 device_type = "pci";
82 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
83 reg = <0x0800 0 0 0 0>;
84 #address-cells = <3>;
85 #size-cells = <2>;
86 interrupt-names = "intx";
87 interrupts-extended = <&mpic 58>;
88 #interrupt-cells = <1>;
89 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
90 0x81000000 0 0 0x81000000 0x1 0 1 0>;
91 bus-range = <0x00 0xff>;
92 interrupt-map-mask = <0 0 0 7>;
93 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
94 <0 0 0 2 &pcie1_intc 1>,
95 <0 0 0 3 &pcie1_intc 2>,
96 <0 0 0 4 &pcie1_intc 3>;
97 marvell,pcie-port = <0>;
98 marvell,pcie-lane = <0>;
99 clocks = <&gateclk 5>;
100 status = "disabled";
101
102 pcie1_intc: interrupt-controller {
103 interrupt-controller;
104 #interrupt-cells = <1>;
105 };
106 };
107
108 pcie2: pcie@2,0 {
109 device_type = "pci";
110 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
111 reg = <0x1000 0 0 0 0>;
112 #address-cells = <3>;
113 #size-cells = <2>;
114 interrupt-names = "intx";
115 interrupts-extended = <&mpic 59>;
116 #interrupt-cells = <1>;
117 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
118 0x81000000 0 0 0x81000000 0x2 0 1 0>;
119 bus-range = <0x00 0xff>;
120 interrupt-map-mask = <0 0 0 7>;
121 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
122 <0 0 0 2 &pcie2_intc 1>,
123 <0 0 0 3 &pcie2_intc 2>,
124 <0 0 0 4 &pcie2_intc 3>;
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <1>;
127 clocks = <&gateclk 6>;
128 status = "disabled";
129
130 pcie2_intc: interrupt-controller {
131 interrupt-controller;
132 #interrupt-cells = <1>;
133 };
134 };
135
136 pcie3: pcie@3,0 {
137 device_type = "pci";
138 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 interrupt-names = "intx";
143 interrupts-extended = <&mpic 60>;
144 #interrupt-cells = <1>;
145 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
146 0x81000000 0 0 0x81000000 0x3 0 1 0>;
147 bus-range = <0x00 0xff>;
148 interrupt-map-mask = <0 0 0 7>;
149 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
150 <0 0 0 2 &pcie3_intc 1>,
151 <0 0 0 3 &pcie3_intc 2>,
152 <0 0 0 4 &pcie3_intc 3>;
153 marvell,pcie-port = <0>;
154 marvell,pcie-lane = <2>;
155 clocks = <&gateclk 7>;
156 status = "disabled";
157
158 pcie3_intc: interrupt-controller {
159 interrupt-controller;
160 #interrupt-cells = <1>;
161 };
162 };
163
164 pcie4: pcie@4,0 {
165 device_type = "pci";
166 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
167 reg = <0x2000 0 0 0 0>;
168 #address-cells = <3>;
169 #size-cells = <2>;
170 interrupt-names = "intx";
171 interrupts-extended = <&mpic 61>;
172 #interrupt-cells = <1>;
173 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
174 0x81000000 0 0 0x81000000 0x4 0 1 0>;
175 bus-range = <0x00 0xff>;
176 interrupt-map-mask = <0 0 0 7>;
177 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
178 <0 0 0 2 &pcie4_intc 1>,
179 <0 0 0 3 &pcie4_intc 2>,
180 <0 0 0 4 &pcie4_intc 3>;
181 marvell,pcie-port = <0>;
182 marvell,pcie-lane = <3>;
183 clocks = <&gateclk 8>;
184 status = "disabled";
185
186 pcie4_intc: interrupt-controller {
187 interrupt-controller;
188 #interrupt-cells = <1>;
189 };
190 };
191
192 pcie5: pcie@5,0 {
193 device_type = "pci";
194 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
195 reg = <0x2800 0 0 0 0>;
196 #address-cells = <3>;
197 #size-cells = <2>;
198 interrupt-names = "intx";
199 interrupts-extended = <&mpic 62>;
200 #interrupt-cells = <1>;
201 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
202 0x81000000 0 0 0x81000000 0x5 0 1 0>;
203 bus-range = <0x00 0xff>;
204 interrupt-map-mask = <0 0 0 7>;
205 interrupt-map = <0 0 0 1 &pcie5_intc 0>,
206 <0 0 0 2 &pcie5_intc 1>,
207 <0 0 0 3 &pcie5_intc 2>,
208 <0 0 0 4 &pcie5_intc 3>;
209 marvell,pcie-port = <1>;
210 marvell,pcie-lane = <0>;
211 clocks = <&gateclk 9>;
212 status = "disabled";
213
214 pcie5_intc: interrupt-controller {
215 interrupt-controller;
216 #interrupt-cells = <1>;
217 };
218 };
219 };
220
221 internal-regs {
222 gpio0: gpio@18100 {
223 compatible = "marvell,armada-370-gpio",
224 "marvell,orion-gpio";
225 reg = <0x18100 0x40>, <0x181c0 0x08>;
226 reg-names = "gpio", "pwm";
227 ngpios = <32>;
228 gpio-controller;
229 #gpio-cells = <2>;
230 #pwm-cells = <2>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
233 interrupts = <82>, <83>, <84>, <85>;
234 clocks = <&coreclk 0>;
235 };
236
237 gpio1: gpio@18140 {
238 compatible = "marvell,armada-370-gpio",
239 "marvell,orion-gpio";
240 reg = <0x18140 0x40>, <0x181c8 0x08>;
241 reg-names = "gpio", "pwm";
242 ngpios = <17>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 #pwm-cells = <2>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
248 interrupts = <87>, <88>, <89>;
249 clocks = <&coreclk 0>;
250 };
251 };
252 };
253 };
254
255 &pinctrl {
256 compatible = "marvell,mv78230-pinctrl";
257 };
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