1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Marvell Technology Group Ltd.
4 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
5 */
6
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
10
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 i2c0 = &twsi1;
21 i2c1 = &twsi2;
22 };
23
24 soc {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
29 ranges;
30
31 L2: l2-cache {
32 compatible = "marvell,tauros2-cache";
33 marvell,tauros2-cache-features = <0x3>;
34 };
35
36 axi@d4200000 { /* AXI */
37 compatible = "mrvl,axi-bus", "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0xd4200000 0x00200000>;
41 ranges;
42
43 gpu: gpu@d420d000 {
44 compatible = "vivante,gc";
45 reg = <0xd420d000 0x4000>;
46 interrupts = <8>;
47 status = "disabled";
48 clocks = <&soc_clocks MMP2_CLK_GPU_3D>,
49 <&soc_clocks MMP2_CLK_GPU_BUS>;
50 clock-names = "core", "bus";
51 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
52 };
53
54 intc: interrupt-controller@d4282000 {
55 compatible = "mrvl,mmp2-intc";
56 interrupt-controller;
57 #interrupt-cells = <1>;
58 reg = <0xd4282000 0x1000>;
59 mrvl,intc-nr-irqs = <64>;
60 };
61
62 intcmux4: interrupt-controller@d4282150 {
63 compatible = "mrvl,mmp2-mux-intc";
64 interrupts = <4>;
65 interrupt-controller;
66 #interrupt-cells = <1>;
67 reg = <0x150 0x4>, <0x168 0x4>;
68 reg-names = "mux status", "mux mask";
69 mrvl,intc-nr-irqs = <2>;
70 };
71
72 intcmux5: interrupt-controller@d4282154 {
73 compatible = "mrvl,mmp2-mux-intc";
74 interrupts = <5>;
75 interrupt-controller;
76 #interrupt-cells = <1>;
77 reg = <0x154 0x4>, <0x16c 0x4>;
78 reg-names = "mux status", "mux mask";
79 mrvl,intc-nr-irqs = <2>;
80 mrvl,clr-mfp-irq = <1>;
81 };
82
83 intcmux9: interrupt-controller@d4282180 {
84 compatible = "mrvl,mmp2-mux-intc";
85 interrupts = <9>;
86 interrupt-controller;
87 #interrupt-cells = <1>;
88 reg = <0x180 0x4>, <0x17c 0x4>;
89 reg-names = "mux status", "mux mask";
90 mrvl,intc-nr-irqs = <3>;
91 };
92
93 intcmux17: interrupt-controller@d4282158 {
94 compatible = "mrvl,mmp2-mux-intc";
95 interrupts = <17>;
96 interrupt-controller;
97 #interrupt-cells = <1>;
98 reg = <0x158 0x4>, <0x170 0x4>;
99 reg-names = "mux status", "mux mask";
100 mrvl,intc-nr-irqs = <5>;
101 };
102
103 intcmux35: interrupt-controller@d428215c {
104 compatible = "mrvl,mmp2-mux-intc";
105 interrupts = <35>;
106 interrupt-controller;
107 #interrupt-cells = <1>;
108 reg = <0x15c 0x4>, <0x174 0x4>;
109 reg-names = "mux status", "mux mask";
110 mrvl,intc-nr-irqs = <15>;
111 };
112
113 intcmux51: interrupt-controller@d4282160 {
114 compatible = "mrvl,mmp2-mux-intc";
115 interrupts = <51>;
116 interrupt-controller;
117 #interrupt-cells = <1>;
118 reg = <0x160 0x4>, <0x178 0x4>;
119 reg-names = "mux status", "mux mask";
120 mrvl,intc-nr-irqs = <2>;
121 };
122
123 intcmux55: interrupt-controller@d4282188 {
124 compatible = "mrvl,mmp2-mux-intc";
125 interrupts = <55>;
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 reg = <0x188 0x4>, <0x184 0x4>;
129 reg-names = "mux status", "mux mask";
130 mrvl,intc-nr-irqs = <2>;
131 };
132
133 usb_phy0: usb-phy@d4207000 {
134 compatible = "marvell,mmp2-usb-phy";
135 reg = <0xd4207000 0x40>;
136 #phy-cells = <0>;
137 status = "disabled";
138 };
139
140 usb_otg0: usb-otg@d4208000 {
141 compatible = "marvell,pxau2o-ehci";
142 reg = <0xd4208000 0x200>;
143 interrupts = <44>;
144 clocks = <&soc_clocks MMP2_CLK_USB>;
145 clock-names = "USBCLK";
146 phys = <&usb_phy0>;
147 phy-names = "usb";
148 status = "disabled";
149 };
150
151 mmc1: mmc@d4280000 {
152 compatible = "mrvl,pxav3-mmc";
153 reg = <0xd4280000 0x120>;
154 clocks = <&soc_clocks MMP2_CLK_SDH0>;
155 clock-names = "io";
156 interrupts = <39>;
157 status = "disabled";
158 };
159
160 mmc2: mmc@d4280800 {
161 compatible = "mrvl,pxav3-mmc";
162 reg = <0xd4280800 0x120>;
163 clocks = <&soc_clocks MMP2_CLK_SDH1>;
164 clock-names = "io";
165 interrupts = <52>;
166 status = "disabled";
167 };
168
169 mmc3: mmc@d4281000 {
170 compatible = "mrvl,pxav3-mmc";
171 reg = <0xd4281000 0x120>;
172 clocks = <&soc_clocks MMP2_CLK_SDH2>;
173 clock-names = "io";
174 interrupts = <53>;
175 status = "disabled";
176 };
177
178 mmc4: mmc@d4281800 {
179 compatible = "mrvl,pxav3-mmc";
180 reg = <0xd4281800 0x120>;
181 clocks = <&soc_clocks MMP2_CLK_SDH3>;
182 clock-names = "io";
183 interrupts = <54>;
184 status = "disabled";
185 };
186
187 camera0: camera@d420a000 {
188 compatible = "marvell,mmp2-ccic";
189 reg = <0xd420a000 0x800>;
190 interrupts = <42>;
191 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
192 clock-names = "axi";
193 #clock-cells = <0>;
194 clock-output-names = "mclk";
195 status = "disabled";
196 };
197
198 camera1: camera@d420a800 {
199 compatible = "marvell,mmp2-ccic";
200 reg = <0xd420a800 0x800>;
201 interrupts = <30>;
202 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
203 clock-names = "axi";
204 #clock-cells = <0>;
205 clock-output-names = "mclk";
206 status = "disabled";
207 };
208
209 adma0: dma-controller@d42a0800 {
210 compatible = "marvell,adma-1.0";
211 reg = <0xd42a0800 0x100>;
212 interrupts = <48>;
213 #dma-cells = <1>;
214 asram = <&asram>;
215 iram = <&asram>;
216 status = "disabled";
217 };
218
219 adma1: dma-controller@d42a0900 {
220 compatible = "marvell,adma-1.0";
221 reg = <0xd42a0900 0x100>;
222 interrupts = <48>;
223 #dma-cells = <1>;
224 status = "disabled";
225 };
226
227 audio_clk: clocks@d42a0c30 {
228 compatible = "marvell,mmp2-audio-clock";
229 reg = <0xd42a0c30 0x10>;
230 clock-names = "audio", "vctcxo", "i2s0", "i2s1";
231 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
232 <&soc_clocks MMP2_CLK_VCTCXO>,
233 <&soc_clocks MMP2_CLK_I2S0>,
234 <&soc_clocks MMP2_CLK_I2S1>;
235 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
236 #clock-cells = <1>;
237 status = "disabled";
238 };
239
240 sspa0: audio-controller@d42a0c00 {
241 compatible = "marvell,mmp-sspa";
242 reg = <0xd42a0c00 0x30>,
243 <0xd42a0c80 0x30>;
244 interrupts = <2>;
245 clock-names = "audio", "bitclk";
246 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
247 <&audio_clk MMP2_CLK_AUDIO_SSPA0>;
248 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
249 #sound-dai-cells = <0>;
250 status = "disabled";
251 };
252
253 sspa1: audio-controller@d42a0d00 {
254 compatible = "marvell,mmp-sspa";
255 reg = <0xd42a0d00 0x30>,
256 <0xd42a0d80 0x30>;
257 interrupts = <3>;
258 clock-names = "audio", "bitclk";
259 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
260 <&audio_clk MMP2_CLK_AUDIO_SSPA1>;
261 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
262 #sound-dai-cells = <0>;
263 status = "disabled";
264 };
265 };
266
267 apb@d4000000 { /* APB */
268 compatible = "mrvl,apb-bus", "simple-bus";
269 #address-cells = <1>;
270 #size-cells = <1>;
271 reg = <0xd4000000 0x00200000>;
272 ranges;
273
274 dma-controller@d4000000 {
275 compatible = "marvell,pdma-1.0";
276 reg = <0xd4000000 0x10000>;
277 interrupts = <48>;
278 /* For backwards compatibility: */
279 #dma-channels = <16>;
280 dma-channels = <16>;
281 status = "disabled";
282 };
283
284 timer0: timer@d4014000 {
285 compatible = "mrvl,mmp-timer";
286 reg = <0xd4014000 0x100>;
287 interrupts = <13>;
288 clocks = <&soc_clocks MMP2_CLK_TIMER>;
289 };
290
291 uart1: serial@d4030000 {
292 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
293 reg = <0xd4030000 0x1000>;
294 interrupts = <27>;
295 clocks = <&soc_clocks MMP2_CLK_UART0>;
296 resets = <&soc_clocks MMP2_CLK_UART0>;
297 reg-shift = <2>;
298 status = "disabled";
299 };
300
301 uart2: serial@d4017000 {
302 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
303 reg = <0xd4017000 0x1000>;
304 interrupts = <28>;
305 clocks = <&soc_clocks MMP2_CLK_UART1>;
306 resets = <&soc_clocks MMP2_CLK_UART1>;
307 reg-shift = <2>;
308 status = "disabled";
309 };
310
311 uart3: serial@d4018000 {
312 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
313 reg = <0xd4018000 0x1000>;
314 interrupts = <24>;
315 clocks = <&soc_clocks MMP2_CLK_UART2>;
316 resets = <&soc_clocks MMP2_CLK_UART2>;
317 reg-shift = <2>;
318 status = "disabled";
319 };
320
321 uart4: serial@d4016000 {
322 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
323 reg = <0xd4016000 0x1000>;
324 interrupts = <46>;
325 clocks = <&soc_clocks MMP2_CLK_UART3>;
326 resets = <&soc_clocks MMP2_CLK_UART3>;
327 reg-shift = <2>;
328 status = "disabled";
329 };
330
331 gpio: gpio@d4019000 {
332 compatible = "marvell,mmp2-gpio";
333 #address-cells = <1>;
334 #size-cells = <1>;
335 reg = <0xd4019000 0x1000>;
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupts = <49>;
339 interrupt-names = "gpio_mux";
340 clocks = <&soc_clocks MMP2_CLK_GPIO>;
341 resets = <&soc_clocks MMP2_CLK_GPIO>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 ranges;
345
346 gcb0: gpio@d4019000 {
347 reg = <0xd4019000 0x4>;
348 };
349
350 gcb1: gpio@d4019004 {
351 reg = <0xd4019004 0x4>;
352 };
353
354 gcb2: gpio@d4019008 {
355 reg = <0xd4019008 0x4>;
356 };
357
358 gcb3: gpio@d4019100 {
359 reg = <0xd4019100 0x4>;
360 };
361
362 gcb4: gpio@d4019104 {
363 reg = <0xd4019104 0x4>;
364 };
365
366 gcb5: gpio@d4019108 {
367 reg = <0xd4019108 0x4>;
368 };
369 };
370
371 twsi1: i2c@d4011000 {
372 compatible = "mrvl,mmp-twsi";
373 reg = <0xd4011000 0x1000>;
374 interrupts = <7>;
375 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
376 resets = <&soc_clocks MMP2_CLK_TWSI0>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 mrvl,i2c-fast-mode;
380 status = "disabled";
381 };
382
383 twsi2: i2c@d4031000 {
384 compatible = "mrvl,mmp-twsi";
385 reg = <0xd4031000 0x1000>;
386 interrupt-parent = <&intcmux17>;
387 interrupts = <0>;
388 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
389 resets = <&soc_clocks MMP2_CLK_TWSI1>;
390 #address-cells = <1>;
391 #size-cells = <0>;
392 status = "disabled";
393 };
394
395 twsi3: i2c@d4032000 {
396 compatible = "mrvl,mmp-twsi";
397 reg = <0xd4032000 0x1000>;
398 interrupt-parent = <&intcmux17>;
399 interrupts = <1>;
400 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
401 resets = <&soc_clocks MMP2_CLK_TWSI2>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 status = "disabled";
405 };
406
407 twsi4: i2c@d4033000 {
408 compatible = "mrvl,mmp-twsi";
409 reg = <0xd4033000 0x1000>;
410 interrupt-parent = <&intcmux17>;
411 interrupts = <2>;
412 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
413 resets = <&soc_clocks MMP2_CLK_TWSI3>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 status = "disabled";
417 };
418
419
420 twsi5: i2c@d4033800 {
421 compatible = "mrvl,mmp-twsi";
422 reg = <0xd4033800 0x1000>;
423 interrupt-parent = <&intcmux17>;
424 interrupts = <3>;
425 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
426 resets = <&soc_clocks MMP2_CLK_TWSI4>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 status = "disabled";
430 };
431
432 twsi6: i2c@d4034000 {
433 compatible = "mrvl,mmp-twsi";
434 reg = <0xd4034000 0x1000>;
435 interrupt-parent = <&intcmux17>;
436 interrupts = <4>;
437 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
438 resets = <&soc_clocks MMP2_CLK_TWSI5>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 status = "disabled";
442 };
443
444 rtc: rtc@d4010000 {
445 compatible = "mrvl,mmp-rtc";
446 reg = <0xd4010000 0x1000>;
447 interrupts = <1>, <0>;
448 interrupt-names = "rtc 1Hz", "rtc alarm";
449 interrupt-parent = <&intcmux5>;
450 clocks = <&soc_clocks MMP2_CLK_RTC>;
451 resets = <&soc_clocks MMP2_CLK_RTC>;
452 status = "disabled";
453 };
454
455 ssp1: spi@d4035000 {
456 compatible = "marvell,mmp2-ssp";
457 reg = <0xd4035000 0x1000>;
458 clocks = <&soc_clocks MMP2_CLK_SSP0>;
459 interrupts = <0>;
460 #address-cells = <1>;
461 #size-cells = <0>;
462 status = "disabled";
463 };
464
465 ssp2: spi@d4036000 {
466 compatible = "marvell,mmp2-ssp";
467 reg = <0xd4036000 0x1000>;
468 clocks = <&soc_clocks MMP2_CLK_SSP1>;
469 interrupts = <1>;
470 #address-cells = <1>;
471 #size-cells = <0>;
472 status = "disabled";
473 };
474
475 ssp3: spi@d4037000 {
476 compatible = "marvell,mmp2-ssp";
477 reg = <0xd4037000 0x1000>;
478 clocks = <&soc_clocks MMP2_CLK_SSP2>;
479 interrupts = <20>;
480 #address-cells = <1>;
481 #size-cells = <0>;
482 status = "disabled";
483 };
484
485 ssp4: spi@d4039000 {
486 compatible = "marvell,mmp2-ssp";
487 reg = <0xd4039000 0x1000>;
488 clocks = <&soc_clocks MMP2_CLK_SSP3>;
489 interrupts = <21>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 status = "disabled";
493 };
494 };
495
496 asram: sram@e0000000 {
497 compatible = "mmio-sram";
498 reg = <0xe0000000 0x10000>;
499 ranges = <0 0xe0000000 0x10000>;
500 #address-cells = <1>;
501 #size-cells = <1>;
502 status = "disabled";
503 };
504
505 soc_clocks: clocks {
506 compatible = "marvell,mmp2-clock";
507 reg = <0xd4050000 0x2000>,
508 <0xd4282800 0x400>,
509 <0xd4015000 0x1000>;
510 reg-names = "mpmu", "apmu", "apbc";
511 #clock-cells = <1>;
512 #reset-cells = <1>;
513 #power-domain-cells = <1>;
514 };
515 };
516 };
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