1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Matthias Brugger <matthias.bgg@gmail.com>
5 *
6 */
7
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "mediatek,mt6589";
15 interrupt-parent = <&sysirq>;
16
17 cpus: cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "mediatek,mt6589-smp";
21
22 cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a7";
25 reg = <0x0>;
26 };
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a7";
30 reg = <0x1>;
31 };
32 cpu@2 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a7";
35 reg = <0x2>;
36 };
37 cpu@3 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a7";
40 reg = <0x3>;
41 };
42
43 };
44
45 clocks {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "simple-bus";
49 ranges;
50
51 system_clk: dummy13m {
52 compatible = "fixed-clock";
53 clock-frequency = <13000000>;
54 #clock-cells = <0>;
55 };
56
57 rtc_clk: dummy32k {
58 compatible = "fixed-clock";
59 clock-frequency = <32000>;
60 #clock-cells = <0>;
61 };
62
63 uart_clk: dummy26m {
64 compatible = "fixed-clock";
65 clock-frequency = <26000000>;
66 #clock-cells = <0>;
67 };
68 };
69
70 soc {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "simple-bus";
74 ranges;
75
76 timer: timer@10008000 {
77 compatible = "mediatek,mt6577-timer";
78 reg = <0x10008000 0x80>;
79 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
80 clocks = <&system_clk>, <&rtc_clk>;
81 clock-names = "system-clk", "rtc-clk";
82 };
83
84 sysirq: interrupt-controller@10200100 {
85 compatible = "mediatek,mt6589-sysirq",
86 "mediatek,mt6577-sysirq";
87 interrupt-controller;
88 #interrupt-cells = <3>;
89 interrupt-parent = <&gic>;
90 reg = <0x10200100 0x1c>;
91 };
92
93 gic: interrupt-controller@10211000 {
94 compatible = "arm,cortex-a7-gic";
95 interrupt-controller;
96 #interrupt-cells = <3>;
97 interrupt-parent = <&gic>;
98 reg = <0x10211000 0x1000>,
99 <0x10212000 0x2000>,
100 <0x10214000 0x2000>,
101 <0x10216000 0x2000>;
102 };
103
104 uart0: serial@11006000 {
105 compatible = "mediatek,mt6577-uart";
106 reg = <0x11006000 0x400>;
107 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
108 clocks = <&uart_clk>;
109 status = "disabled";
110 };
111
112 uart1: serial@11007000 {
113 compatible = "mediatek,mt6577-uart";
114 reg = <0x11007000 0x400>;
115 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
116 clocks = <&uart_clk>;
117 status = "disabled";
118 };
119
120 uart2: serial@11008000 {
121 compatible = "mediatek,mt6577-uart";
122 reg = <0x11008000 0x400>;
123 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
124 clocks = <&uart_clk>;
125 status = "disabled";
126 };
127
128 uart3: serial@11009000 {
129 compatible = "mediatek,mt6577-uart";
130 reg = <0x11009000 0x400>;
131 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
132 clocks = <&uart_clk>;
133 status = "disabled";
134 };
135
136 wdt: watchdog@10000000 {
137 compatible = "mediatek,mt6589-wdt";
138 reg = <0x10000000 0x44>;
139 };
140 };
141 };
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