1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 // Copyright 2021 Jonathan Neuschäfer
3
4 #include <dt-bindings/interrupt-controller/irq.h>
5
6 / {
7 compatible = "nuvoton,wpcm450";
8 #address-cells = <1>;
9 #size-cells = <1>;
10
11 aliases {
12 gpio0 = &gpio0;
13 gpio1 = &gpio1;
14 gpio2 = &gpio2;
15 gpio3 = &gpio3;
16 gpio4 = &gpio4;
17 gpio5 = &gpio5;
18 gpio6 = &gpio6;
19 gpio7 = &gpio7;
20 };
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu@0 {
27 compatible = "arm,arm926ej-s";
28 device_type = "cpu";
29 reg = <0>;
30 };
31 };
32
33 clk24m: clock-24mhz {
34 /* 24 MHz dummy clock */
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
37 #clock-cells = <0>;
38 };
39
40 refclk: clock-48mhz {
41 /* 48 MHz reference oscillator */
42 compatible = "fixed-clock";
43 clock-output-names = "ref";
44 clock-frequency = <48000000>;
45 #clock-cells = <0>;
46 };
47
48 soc {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&aic>;
53 ranges;
54
55 gcr: syscon@b0000000 {
56 compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd";
57 reg = <0xb0000000 0x200>;
58 };
59
60 clk: clock-controller@b0000200 {
61 compatible = "nuvoton,wpcm450-clk";
62 reg = <0xb0000200 0x100>;
63 clocks = <&refclk>;
64 clock-names = "ref";
65 #clock-cells = <1>;
66 #reset-cells = <1>;
67 };
68
69 serial0: serial@b8000000 {
70 compatible = "nuvoton,wpcm450-uart";
71 reg = <0xb8000000 0x20>;
72 reg-shift = <2>;
73 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&clk24m>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&bsp_pins>;
77 status = "disabled";
78 };
79
80 serial1: serial@b8000100 {
81 compatible = "nuvoton,wpcm450-uart";
82 reg = <0xb8000100 0x20>;
83 reg-shift = <2>;
84 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&clk24m>;
86 status = "disabled";
87 };
88
89 timer0: timer@b8001000 {
90 compatible = "nuvoton,wpcm450-timer";
91 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
92 reg = <0xb8001000 0x1c>;
93 clocks = <&clk24m>;
94 };
95
96 watchdog0: watchdog@b800101c {
97 compatible = "nuvoton,wpcm450-wdt";
98 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
99 reg = <0xb800101c 0x4>;
100 clocks = <&clk24m>;
101 };
102
103 aic: interrupt-controller@b8002000 {
104 compatible = "nuvoton,wpcm450-aic";
105 reg = <0xb8002000 0x1000>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 };
109
110 pinctrl: pinctrl@b8003000 {
111 compatible = "nuvoton,wpcm450-pinctrl";
112 reg = <0xb8003000 0x1000>;
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 gpio0: gpio@0 {
117 reg = <0>;
118 gpio-controller;
119 #gpio-cells = <2>;
120 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
121 <3 IRQ_TYPE_LEVEL_HIGH>,
122 <4 IRQ_TYPE_LEVEL_HIGH>;
123 #interrupt-cells = <2>;
124 interrupt-controller;
125 };
126
127 gpio1: gpio@1 {
128 reg = <1>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 };
135
136 gpio2: gpio@2 {
137 reg = <2>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 };
141
142 gpio3: gpio@3 {
143 reg = <3>;
144 gpio-controller;
145 #gpio-cells = <2>;
146 };
147
148 gpio4: gpio@4 {
149 reg = <4>;
150 gpio-controller;
151 #gpio-cells = <2>;
152 };
153
154 gpio5: gpio@5 {
155 reg = <5>;
156 gpio-controller;
157 #gpio-cells = <2>;
158 };
159
160 gpio6: gpio@6 {
161 reg = <6>;
162 gpio-controller;
163 #gpio-cells = <2>;
164 };
165
166 gpio7: gpio@7 {
167 reg = <7>;
168 gpio-controller;
169 #gpio-cells = <2>;
170 };
171
172 smb3_pins: mux-smb3 {
173 groups = "smb3";
174 function = "smb3";
175 };
176
177 smb4_pins: mux-smb4 {
178 groups = "smb4";
179 function = "smb4";
180 };
181
182 smb5_pins: mux-smb5 {
183 groups = "smb5";
184 function = "smb5";
185 };
186
187 scs1_pins: mux-scs1 {
188 groups = "scs1";
189 function = "scs1";
190 };
191
192 scs2_pins: mux-scs2 {
193 groups = "scs2";
194 function = "scs2";
195 };
196
197 scs3_pins: mux-scs3 {
198 groups = "scs3";
199 function = "scs3";
200 };
201
202 smb0_pins: mux-smb0 {
203 groups = "smb0";
204 function = "smb0";
205 };
206
207 smb1_pins: mux-smb1 {
208 groups = "smb1";
209 function = "smb1";
210 };
211
212 smb2_pins: mux-smb2 {
213 groups = "smb2";
214 function = "smb2";
215 };
216
217 bsp_pins: mux-bsp {
218 groups = "bsp";
219 function = "bsp";
220 };
221
222 hsp1_pins: mux-hsp1 {
223 groups = "hsp1";
224 function = "hsp1";
225 };
226
227 hsp2_pins: mux-hsp2 {
228 groups = "hsp2";
229 function = "hsp2";
230 };
231
232 r1err_pins: mux-r1err {
233 groups = "r1err";
234 function = "r1err";
235 };
236
237 r1md_pins: mux-r1md {
238 groups = "r1md";
239 function = "r1md";
240 };
241
242 rmii2_pins: mux-rmii2 {
243 groups = "rmii2";
244 function = "rmii2";
245 };
246
247 r2err_pins: mux-r2err {
248 groups = "r2err";
249 function = "r2err";
250 };
251
252 r2md_pins: mux-r2md {
253 groups = "r2md";
254 function = "r2md";
255 };
256
257 kbcc_pins: mux-kbcc {
258 groups = "kbcc";
259 function = "kbcc";
260 };
261
262 dvo0_pins: mux-dvo0 {
263 groups = "dvo";
264 function = "dvo0";
265 };
266
267 dvo3_pins: mux-dvo3 {
268 groups = "dvo";
269 function = "dvo3";
270 };
271
272 clko_pins: mux-clko {
273 groups = "clko";
274 function = "clko";
275 };
276
277 smi_pins: mux-smi {
278 groups = "smi";
279 function = "smi";
280 };
281
282 uinc_pins: mux-uinc {
283 groups = "uinc";
284 function = "uinc";
285 };
286
287 gspi_pins: mux-gspi {
288 groups = "gspi";
289 function = "gspi";
290 };
291
292 mben_pins: mux-mben {
293 groups = "mben";
294 function = "mben";
295 };
296
297 xcs2_pins: mux-xcs2 {
298 groups = "xcs2";
299 function = "xcs2";
300 };
301
302 xcs1_pins: mux-xcs1 {
303 groups = "xcs1";
304 function = "xcs1";
305 };
306
307 sdio_pins: mux-sdio {
308 groups = "sdio";
309 function = "sdio";
310 };
311
312 sspi_pins: mux-sspi {
313 groups = "sspi";
314 function = "sspi";
315 };
316
317 fi0_pins: mux-fi0 {
318 groups = "fi0";
319 function = "fi0";
320 };
321
322 fi1_pins: mux-fi1 {
323 groups = "fi1";
324 function = "fi1";
325 };
326
327 fi2_pins: mux-fi2 {
328 groups = "fi2";
329 function = "fi2";
330 };
331
332 fi3_pins: mux-fi3 {
333 groups = "fi3";
334 function = "fi3";
335 };
336
337 fi4_pins: mux-fi4 {
338 groups = "fi4";
339 function = "fi4";
340 };
341
342 fi5_pins: mux-fi5 {
343 groups = "fi5";
344 function = "fi5";
345 };
346
347 fi6_pins: mux-fi6 {
348 groups = "fi6";
349 function = "fi6";
350 };
351
352 fi7_pins: mux-fi7 {
353 groups = "fi7";
354 function = "fi7";
355 };
356
357 fi8_pins: mux-fi8 {
358 groups = "fi8";
359 function = "fi8";
360 };
361
362 fi9_pins: mux-fi9 {
363 groups = "fi9";
364 function = "fi9";
365 };
366
367 fi10_pins: mux-fi10 {
368 groups = "fi10";
369 function = "fi10";
370 };
371
372 fi11_pins: mux-fi11 {
373 groups = "fi11";
374 function = "fi11";
375 };
376
377 fi12_pins: mux-fi12 {
378 groups = "fi12";
379 function = "fi12";
380 };
381
382 fi13_pins: mux-fi13 {
383 groups = "fi13";
384 function = "fi13";
385 };
386
387 fi14_pins: mux-fi14 {
388 groups = "fi14";
389 function = "fi14";
390 };
391
392 fi15_pins: mux-fi15 {
393 groups = "fi15";
394 function = "fi15";
395 };
396
397 pwm0_pins: mux-pwm0 {
398 groups = "pwm0";
399 function = "pwm0";
400 };
401
402 pwm1_pins: mux-pwm1 {
403 groups = "pwm1";
404 function = "pwm1";
405 };
406
407 pwm2_pins: mux-pwm2 {
408 groups = "pwm2";
409 function = "pwm2";
410 };
411
412 pwm3_pins: mux-pwm3 {
413 groups = "pwm3";
414 function = "pwm3";
415 };
416
417 pwm4_pins: mux-pwm4 {
418 groups = "pwm4";
419 function = "pwm4";
420 };
421
422 pwm5_pins: mux-pwm5 {
423 groups = "pwm5";
424 function = "pwm5";
425 };
426
427 pwm6_pins: mux-pwm6 {
428 groups = "pwm6";
429 function = "pwm6";
430 };
431
432 pwm7_pins: mux-pwm7 {
433 groups = "pwm7";
434 function = "pwm7";
435 };
436
437 hg0_pins: mux-hg0 {
438 groups = "hg0";
439 function = "hg0";
440 };
441
442 hg1_pins: mux-hg1 {
443 groups = "hg1";
444 function = "hg1";
445 };
446
447 hg2_pins: mux-hg2 {
448 groups = "hg2";
449 function = "hg2";
450 };
451
452 hg3_pins: mux-hg3 {
453 groups = "hg3";
454 function = "hg3";
455 };
456
457 hg4_pins: mux-hg4 {
458 groups = "hg4";
459 function = "hg4";
460 };
461
462 hg5_pins: mux-hg5 {
463 groups = "hg5";
464 function = "hg5";
465 };
466
467 hg6_pins: mux-hg6 {
468 groups = "hg6";
469 function = "hg6";
470 };
471
472 hg7_pins: mux-hg7 {
473 groups = "hg7";
474 function = "hg7";
475 };
476 };
477
478 fiu: spi-controller@c8000000 {
479 compatible = "nuvoton,wpcm450-fiu";
480 #address-cells = <1>;
481 #size-cells = <0>;
482 reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
483 reg-names = "control", "memory";
484 clocks = <&clk 0>;
485 nuvoton,shm = <&shm>;
486 status = "disabled";
487 };
488
489 shm: syscon@c8001000 {
490 compatible = "nuvoton,wpcm450-shm", "syscon";
491 reg = <0xc8001000 0x1000>;
492 reg-io-width = <1>;
493 };
494 };
495 };
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