1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8
9 / {
10 compatible = "nvidia,tegra114";
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 memory@80000000 {
16 device_type = "memory";
17 reg = <0x80000000 0x0>;
18 };
19
20 sram@40000000 {
21 compatible = "mmio-sram";
22 reg = <0x40000000 0x40000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges = <0 0x40000000 0x40000>;
26
27 vde_pool: sram@400 {
28 reg = <0x400 0x3fc00>;
29 pool;
30 };
31 };
32
33 host1x@50000000 {
34 compatible = "nvidia,tegra114-host1x";
35 reg = <0x50000000 0x00028000>;
36 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
37 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
38 interrupt-names = "syncpt", "host1x";
39 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
40 clock-names = "host1x";
41 resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>;
42 reset-names = "host1x", "mc";
43 iommus = <&mc TEGRA_SWGROUP_HC>;
44
45 #address-cells = <1>;
46 #size-cells = <1>;
47
48 ranges = <0x54000000 0x54000000 0x01000000>;
49
50 gr2d@54140000 {
51 compatible = "nvidia,tegra114-gr2d";
52 reg = <0x54140000 0x00040000>;
53 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
55 resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>;
56 reset-names = "2d", "mc";
57
58 iommus = <&mc TEGRA_SWGROUP_G2>;
59 };
60
61 gr3d@54180000 {
62 compatible = "nvidia,tegra114-gr3d";
63 reg = <0x54180000 0x00040000>;
64 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
65 resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>;
66 reset-names = "3d", "mc";
67
68 iommus = <&mc TEGRA_SWGROUP_NV>;
69 };
70
71 dc@54200000 {
72 compatible = "nvidia,tegra114-dc";
73 reg = <0x54200000 0x00040000>;
74 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
75 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
76 <&tegra_car TEGRA114_CLK_PLL_P>;
77 clock-names = "dc", "parent";
78 resets = <&tegra_car 27>;
79 reset-names = "dc";
80
81 iommus = <&mc TEGRA_SWGROUP_DC>;
82
83 nvidia,head = <0>;
84
85 rgb {
86 status = "disabled";
87 };
88 };
89
90 dc@54240000 {
91 compatible = "nvidia,tegra114-dc";
92 reg = <0x54240000 0x00040000>;
93 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
95 <&tegra_car TEGRA114_CLK_PLL_P>;
96 clock-names = "dc", "parent";
97 resets = <&tegra_car 26>;
98 reset-names = "dc";
99
100 iommus = <&mc TEGRA_SWGROUP_DCB>;
101
102 nvidia,head = <1>;
103
104 rgb {
105 status = "disabled";
106 };
107 };
108
109 hdmi@54280000 {
110 compatible = "nvidia,tegra114-hdmi";
111 reg = <0x54280000 0x00040000>;
112 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
114 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
115 clock-names = "hdmi", "parent";
116 resets = <&tegra_car 51>;
117 reset-names = "hdmi";
118 status = "disabled";
119 };
120
121 dsia: dsi@54300000 {
122 compatible = "nvidia,tegra114-dsi";
123 reg = <0x54300000 0x00040000>;
124 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
125 <&tegra_car TEGRA114_CLK_DSIALP>,
126 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
127 clock-names = "dsi", "lp", "parent";
128 resets = <&tegra_car 48>;
129 reset-names = "dsi";
130 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
131 status = "disabled";
132
133 #address-cells = <1>;
134 #size-cells = <0>;
135 };
136
137 dsib: dsi@54400000 {
138 compatible = "nvidia,tegra114-dsi";
139 reg = <0x54400000 0x00040000>;
140 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
141 <&tegra_car TEGRA114_CLK_DSIBLP>,
142 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
143 clock-names = "dsi", "lp", "parent";
144 resets = <&tegra_car 82>;
145 reset-names = "dsi";
146 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
147 status = "disabled";
148
149 #address-cells = <1>;
150 #size-cells = <0>;
151 };
152 };
153
154 gic: interrupt-controller@50041000 {
155 compatible = "arm,cortex-a15-gic";
156 #interrupt-cells = <3>;
157 interrupt-controller;
158 reg = <0x50041000 0x1000>,
159 <0x50042000 0x1000>,
160 <0x50044000 0x2000>,
161 <0x50046000 0x2000>;
162 interrupts = <GIC_PPI 9
163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
164 interrupt-parent = <&gic>;
165 };
166
167 lic: interrupt-controller@60004000 {
168 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
169 reg = <0x60004000 0x100>,
170 <0x60004100 0x50>,
171 <0x60004200 0x50>,
172 <0x60004300 0x50>,
173 <0x60004400 0x50>;
174 interrupt-controller;
175 #interrupt-cells = <3>;
176 interrupt-parent = <&gic>;
177 };
178
179 timer@60005000 {
180 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer";
181 reg = <0x60005000 0x400>;
182 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
189 };
190
191 tegra_car: clock@60006000 {
192 compatible = "nvidia,tegra114-car";
193 reg = <0x60006000 0x1000>;
194 #clock-cells = <1>;
195 #reset-cells = <1>;
196 };
197
198 flow-controller@60007000 {
199 compatible = "nvidia,tegra114-flowctrl";
200 reg = <0x60007000 0x1000>;
201 };
202
203 apbdma: dma@6000a000 {
204 compatible = "nvidia,tegra114-apbdma";
205 reg = <0x6000a000 0x1400>;
206 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
239 resets = <&tegra_car 34>;
240 reset-names = "dma";
241 #dma-cells = <1>;
242 };
243
244 ahb: ahb@6000c000 {
245 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
246 reg = <0x6000c000 0x150>;
247 };
248
249 gpio: gpio@6000d000 {
250 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
251 reg = <0x6000d000 0x1000>;
252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
260 #gpio-cells = <2>;
261 gpio-controller;
262 #interrupt-cells = <2>;
263 interrupt-controller;
264 gpio-ranges = <&pinmux 0 0 246>;
265 };
266
267 vde@6001a000 {
268 compatible = "nvidia,tegra114-vde";
269 reg = <0x6001a000 0x1000>, /* Syntax Engine */
270 <0x6001b000 0x1000>, /* Video Bitstream Engine */
271 <0x6001c000 0x100>, /* Macroblock Engine */
272 <0x6001c200 0x100>, /* Post-processing Engine */
273 <0x6001c400 0x100>, /* Motion Compensation Engine */
274 <0x6001c600 0x100>, /* Transform Engine */
275 <0x6001c800 0x100>, /* Pixel prediction block */
276 <0x6001ca00 0x100>, /* Video DMA */
277 <0x6001d800 0x400>; /* Video frame controls */
278 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
279 "tfe", "ppb", "vdma", "frameid";
280 iram = <&vde_pool>; /* IRAM region */
281 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
282 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
283 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
284 interrupt-names = "sync-token", "bsev", "sxe";
285 clocks = <&tegra_car TEGRA114_CLK_VDE>;
286 reset-names = "vde", "mc";
287 resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>;
288 iommus = <&mc TEGRA_SWGROUP_VDE>;
289 };
290
291 apbmisc@70000800 {
292 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
293 reg = <0x70000800 0x64>, /* Chip revision */
294 <0x70000008 0x04>; /* Strapping options */
295 };
296
297 pinmux: pinmux@70000868 {
298 compatible = "nvidia,tegra114-pinmux";
299 reg = <0x70000868 0x148>, /* Pad control registers */
300 <0x70003000 0x40c>; /* Mux registers */
301 };
302
303 /*
304 * There are two serial driver i.e. 8250 based simple serial
305 * driver and APB DMA based serial driver for higher baudrate
306 * and performace. To enable the 8250 based driver, the compatible
307 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
308 * the APB DMA based serial driver, the compatible is
309 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
310 */
311 uarta: serial@70006000 {
312 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
313 reg = <0x70006000 0x40>;
314 reg-shift = <2>;
315 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
317 resets = <&tegra_car 6>;
318 dmas = <&apbdma 8>, <&apbdma 8>;
319 dma-names = "rx", "tx";
320 status = "disabled";
321 };
322
323 uartb: serial@70006040 {
324 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
325 reg = <0x70006040 0x40>;
326 reg-shift = <2>;
327 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
329 resets = <&tegra_car 7>;
330 dmas = <&apbdma 9>, <&apbdma 9>;
331 dma-names = "rx", "tx";
332 status = "disabled";
333 };
334
335 uartc: serial@70006200 {
336 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
337 reg = <0x70006200 0x100>;
338 reg-shift = <2>;
339 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
341 resets = <&tegra_car 55>;
342 dmas = <&apbdma 10>, <&apbdma 10>;
343 dma-names = "rx", "tx";
344 status = "disabled";
345 };
346
347 uartd: serial@70006300 {
348 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
349 reg = <0x70006300 0x100>;
350 reg-shift = <2>;
351 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
353 resets = <&tegra_car 65>;
354 dmas = <&apbdma 19>, <&apbdma 19>;
355 dma-names = "rx", "tx";
356 status = "disabled";
357 };
358
359 pwm: pwm@7000a000 {
360 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
361 reg = <0x7000a000 0x100>;
362 #pwm-cells = <2>;
363 clocks = <&tegra_car TEGRA114_CLK_PWM>;
364 resets = <&tegra_car 17>;
365 reset-names = "pwm";
366 status = "disabled";
367 };
368
369 i2c@7000c000 {
370 compatible = "nvidia,tegra114-i2c";
371 reg = <0x7000c000 0x100>;
372 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
373 #address-cells = <1>;
374 #size-cells = <0>;
375 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
376 clock-names = "div-clk";
377 resets = <&tegra_car 12>;
378 reset-names = "i2c";
379 dmas = <&apbdma 21>, <&apbdma 21>;
380 dma-names = "rx", "tx";
381 status = "disabled";
382 };
383
384 i2c@7000c400 {
385 compatible = "nvidia,tegra114-i2c";
386 reg = <0x7000c400 0x100>;
387 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
388 #address-cells = <1>;
389 #size-cells = <0>;
390 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
391 clock-names = "div-clk";
392 resets = <&tegra_car 54>;
393 reset-names = "i2c";
394 dmas = <&apbdma 22>, <&apbdma 22>;
395 dma-names = "rx", "tx";
396 status = "disabled";
397 };
398
399 i2c@7000c500 {
400 compatible = "nvidia,tegra114-i2c";
401 reg = <0x7000c500 0x100>;
402 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
406 clock-names = "div-clk";
407 resets = <&tegra_car 67>;
408 reset-names = "i2c";
409 dmas = <&apbdma 23>, <&apbdma 23>;
410 dma-names = "rx", "tx";
411 status = "disabled";
412 };
413
414 i2c@7000c700 {
415 compatible = "nvidia,tegra114-i2c";
416 reg = <0x7000c700 0x100>;
417 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
421 clock-names = "div-clk";
422 resets = <&tegra_car 103>;
423 reset-names = "i2c";
424 dmas = <&apbdma 26>, <&apbdma 26>;
425 dma-names = "rx", "tx";
426 status = "disabled";
427 };
428
429 i2c@7000d000 {
430 compatible = "nvidia,tegra114-i2c";
431 reg = <0x7000d000 0x100>;
432 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
436 clock-names = "div-clk";
437 resets = <&tegra_car 47>;
438 reset-names = "i2c";
439 dmas = <&apbdma 24>, <&apbdma 24>;
440 dma-names = "rx", "tx";
441 status = "disabled";
442 };
443
444 spi@7000d400 {
445 compatible = "nvidia,tegra114-spi";
446 reg = <0x7000d400 0x200>;
447 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
451 clock-names = "spi";
452 resets = <&tegra_car 41>;
453 reset-names = "spi";
454 dmas = <&apbdma 15>, <&apbdma 15>;
455 dma-names = "rx", "tx";
456 status = "disabled";
457 };
458
459 spi@7000d600 {
460 compatible = "nvidia,tegra114-spi";
461 reg = <0x7000d600 0x200>;
462 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
466 clock-names = "spi";
467 resets = <&tegra_car 44>;
468 reset-names = "spi";
469 dmas = <&apbdma 16>, <&apbdma 16>;
470 dma-names = "rx", "tx";
471 status = "disabled";
472 };
473
474 spi@7000d800 {
475 compatible = "nvidia,tegra114-spi";
476 reg = <0x7000d800 0x200>;
477 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
481 clock-names = "spi";
482 resets = <&tegra_car 46>;
483 reset-names = "spi";
484 dmas = <&apbdma 17>, <&apbdma 17>;
485 dma-names = "rx", "tx";
486 status = "disabled";
487 };
488
489 spi@7000da00 {
490 compatible = "nvidia,tegra114-spi";
491 reg = <0x7000da00 0x200>;
492 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
493 #address-cells = <1>;
494 #size-cells = <0>;
495 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
496 clock-names = "spi";
497 resets = <&tegra_car 68>;
498 reset-names = "spi";
499 dmas = <&apbdma 18>, <&apbdma 18>;
500 dma-names = "rx", "tx";
501 status = "disabled";
502 };
503
504 spi@7000dc00 {
505 compatible = "nvidia,tegra114-spi";
506 reg = <0x7000dc00 0x200>;
507 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
511 clock-names = "spi";
512 resets = <&tegra_car 104>;
513 reset-names = "spi";
514 dmas = <&apbdma 27>, <&apbdma 27>;
515 dma-names = "rx", "tx";
516 status = "disabled";
517 };
518
519 spi@7000de00 {
520 compatible = "nvidia,tegra114-spi";
521 reg = <0x7000de00 0x200>;
522 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
526 clock-names = "spi";
527 resets = <&tegra_car 105>;
528 reset-names = "spi";
529 dmas = <&apbdma 28>, <&apbdma 28>;
530 dma-names = "rx", "tx";
531 status = "disabled";
532 };
533
534 rtc@7000e000 {
535 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
536 reg = <0x7000e000 0x100>;
537 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&tegra_car TEGRA114_CLK_RTC>;
539 };
540
541 kbc@7000e200 {
542 compatible = "nvidia,tegra114-kbc";
543 reg = <0x7000e200 0x100>;
544 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&tegra_car TEGRA114_CLK_KBC>;
546 resets = <&tegra_car 36>;
547 reset-names = "kbc";
548 status = "disabled";
549 };
550
551 tegra_pmc: pmc@7000e400 {
552 compatible = "nvidia,tegra114-pmc";
553 reg = <0x7000e400 0x400>;
554 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
555 clock-names = "pclk", "clk32k_in";
556 #clock-cells = <1>;
557 };
558
559 fuse@7000f800 {
560 compatible = "nvidia,tegra114-efuse";
561 reg = <0x7000f800 0x400>;
562 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
563 clock-names = "fuse";
564 resets = <&tegra_car 39>;
565 reset-names = "fuse";
566 };
567
568 mc: memory-controller@70019000 {
569 compatible = "nvidia,tegra114-mc";
570 reg = <0x70019000 0x1000>;
571 clocks = <&tegra_car TEGRA114_CLK_MC>;
572 clock-names = "mc";
573
574 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
575
576 #reset-cells = <1>;
577 #iommu-cells = <1>;
578 };
579
580 ahub@70080000 {
581 compatible = "nvidia,tegra114-ahub";
582 reg = <0x70080000 0x200>,
583 <0x70080200 0x100>,
584 <0x70081000 0x200>;
585 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
587 <&tegra_car TEGRA114_CLK_APBIF>;
588 clock-names = "d_audio", "apbif";
589 resets = <&tegra_car 106>, /* d_audio */
590 <&tegra_car 107>, /* apbif */
591 <&tegra_car 30>, /* i2s0 */
592 <&tegra_car 11>, /* i2s1 */
593 <&tegra_car 18>, /* i2s2 */
594 <&tegra_car 101>, /* i2s3 */
595 <&tegra_car 102>, /* i2s4 */
596 <&tegra_car 108>, /* dam0 */
597 <&tegra_car 109>, /* dam1 */
598 <&tegra_car 110>, /* dam2 */
599 <&tegra_car 10>, /* spdif */
600 <&tegra_car 153>, /* amx */
601 <&tegra_car 154>; /* adx */
602 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
603 "i2s3", "i2s4", "dam0", "dam1", "dam2",
604 "spdif", "amx", "adx";
605 dmas = <&apbdma 1>, <&apbdma 1>,
606 <&apbdma 2>, <&apbdma 2>,
607 <&apbdma 3>, <&apbdma 3>,
608 <&apbdma 4>, <&apbdma 4>,
609 <&apbdma 6>, <&apbdma 6>,
610 <&apbdma 7>, <&apbdma 7>,
611 <&apbdma 12>, <&apbdma 12>,
612 <&apbdma 13>, <&apbdma 13>,
613 <&apbdma 14>, <&apbdma 14>,
614 <&apbdma 29>, <&apbdma 29>;
615 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
616 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
617 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
618 "rx9", "tx9";
619 ranges;
620 #address-cells = <1>;
621 #size-cells = <1>;
622
623 tegra_i2s0: i2s@70080300 {
624 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
625 reg = <0x70080300 0x100>;
626 nvidia,ahub-cif-ids = <4 4>;
627 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
628 resets = <&tegra_car 30>;
629 reset-names = "i2s";
630 status = "disabled";
631 };
632
633 tegra_i2s1: i2s@70080400 {
634 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
635 reg = <0x70080400 0x100>;
636 nvidia,ahub-cif-ids = <5 5>;
637 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
638 resets = <&tegra_car 11>;
639 reset-names = "i2s";
640 status = "disabled";
641 };
642
643 tegra_i2s2: i2s@70080500 {
644 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
645 reg = <0x70080500 0x100>;
646 nvidia,ahub-cif-ids = <6 6>;
647 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
648 resets = <&tegra_car 18>;
649 reset-names = "i2s";
650 status = "disabled";
651 };
652
653 tegra_i2s3: i2s@70080600 {
654 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
655 reg = <0x70080600 0x100>;
656 nvidia,ahub-cif-ids = <7 7>;
657 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
658 resets = <&tegra_car 101>;
659 reset-names = "i2s";
660 status = "disabled";
661 };
662
663 tegra_i2s4: i2s@70080700 {
664 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
665 reg = <0x70080700 0x100>;
666 nvidia,ahub-cif-ids = <8 8>;
667 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
668 resets = <&tegra_car 102>;
669 reset-names = "i2s";
670 status = "disabled";
671 };
672 };
673
674 mipi: mipi@700e3000 {
675 compatible = "nvidia,tegra114-mipi";
676 reg = <0x700e3000 0x100>;
677 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
678 #nvidia,mipi-calibrate-cells = <1>;
679 };
680
681 mmc@78000000 {
682 compatible = "nvidia,tegra114-sdhci";
683 reg = <0x78000000 0x200>;
684 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
686 clock-names = "sdhci";
687 resets = <&tegra_car 14>;
688 reset-names = "sdhci";
689 status = "disabled";
690 };
691
692 mmc@78000200 {
693 compatible = "nvidia,tegra114-sdhci";
694 reg = <0x78000200 0x200>;
695 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
697 clock-names = "sdhci";
698 resets = <&tegra_car 9>;
699 reset-names = "sdhci";
700 status = "disabled";
701 };
702
703 mmc@78000400 {
704 compatible = "nvidia,tegra114-sdhci";
705 reg = <0x78000400 0x200>;
706 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
708 clock-names = "sdhci";
709 resets = <&tegra_car 69>;
710 reset-names = "sdhci";
711 status = "disabled";
712 };
713
714 mmc@78000600 {
715 compatible = "nvidia,tegra114-sdhci";
716 reg = <0x78000600 0x200>;
717 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
719 clock-names = "sdhci";
720 resets = <&tegra_car 15>;
721 reset-names = "sdhci";
722 status = "disabled";
723 };
724
725 usb@7d000000 {
726 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
727 reg = <0x7d000000 0x4000>;
728 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
729 phy_type = "utmi";
730 clocks = <&tegra_car TEGRA114_CLK_USBD>;
731 resets = <&tegra_car 22>;
732 reset-names = "usb";
733 nvidia,phy = <&phy1>;
734 status = "disabled";
735 };
736
737 phy1: usb-phy@7d000000 {
738 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
739 reg = <0x7d000000 0x4000>,
740 <0x7d000000 0x4000>;
741 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
742 phy_type = "utmi";
743 clocks = <&tegra_car TEGRA114_CLK_USBD>,
744 <&tegra_car TEGRA114_CLK_PLL_U>,
745 <&tegra_car TEGRA114_CLK_USBD>;
746 clock-names = "reg", "pll_u", "utmi-pads";
747 resets = <&tegra_car 22>, <&tegra_car 22>;
748 reset-names = "usb", "utmi-pads";
749 #phy-cells = <0>;
750 nvidia,hssync-start-delay = <0>;
751 nvidia,idle-wait-delay = <17>;
752 nvidia,elastic-limit = <16>;
753 nvidia,term-range-adj = <6>;
754 nvidia,xcvr-setup = <9>;
755 nvidia,xcvr-lsfslew = <0>;
756 nvidia,xcvr-lsrslew = <3>;
757 nvidia,hssquelch-level = <2>;
758 nvidia,hsdiscon-level = <5>;
759 nvidia,xcvr-hsslew = <12>;
760 nvidia,has-utmi-pad-registers;
761 nvidia,pmc = <&tegra_pmc 0>;
762 status = "disabled";
763 };
764
765 usb@7d008000 {
766 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
767 reg = <0x7d008000 0x4000>;
768 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
769 phy_type = "utmi";
770 clocks = <&tegra_car TEGRA114_CLK_USB3>;
771 resets = <&tegra_car 59>;
772 reset-names = "usb";
773 nvidia,phy = <&phy3>;
774 status = "disabled";
775 };
776
777 phy3: usb-phy@7d008000 {
778 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
779 reg = <0x7d008000 0x4000>,
780 <0x7d000000 0x4000>;
781 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
782 phy_type = "utmi";
783 clocks = <&tegra_car TEGRA114_CLK_USB3>,
784 <&tegra_car TEGRA114_CLK_PLL_U>,
785 <&tegra_car TEGRA114_CLK_USBD>;
786 clock-names = "reg", "pll_u", "utmi-pads";
787 resets = <&tegra_car 59>, <&tegra_car 22>;
788 reset-names = "usb", "utmi-pads";
789 #phy-cells = <0>;
790 nvidia,hssync-start-delay = <0>;
791 nvidia,idle-wait-delay = <17>;
792 nvidia,elastic-limit = <16>;
793 nvidia,term-range-adj = <6>;
794 nvidia,xcvr-setup = <9>;
795 nvidia,xcvr-lsfslew = <0>;
796 nvidia,xcvr-lsrslew = <3>;
797 nvidia,hssquelch-level = <2>;
798 nvidia,hsdiscon-level = <5>;
799 nvidia,xcvr-hsslew = <12>;
800 nvidia,pmc = <&tegra_pmc 2>;
801 status = "disabled";
802 };
803
804 cpus {
805 #address-cells = <1>;
806 #size-cells = <0>;
807
808 cpu@0 {
809 device_type = "cpu";
810 compatible = "arm,cortex-a15";
811 reg = <0>;
812 };
813
814 cpu@1 {
815 device_type = "cpu";
816 compatible = "arm,cortex-a15";
817 reg = <1>;
818 };
819
820 cpu@2 {
821 device_type = "cpu";
822 compatible = "arm,cortex-a15";
823 reg = <2>;
824 };
825
826 cpu@3 {
827 device_type = "cpu";
828 compatible = "arm,cortex-a15";
829 reg = <3>;
830 };
831 };
832
833 timer {
834 compatible = "arm,armv7-timer";
835 interrupts =
836 <GIC_PPI 13
837 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
838 <GIC_PPI 14
839 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
840 <GIC_PPI 11
841 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
842 <GIC_PPI 10
843 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
844 interrupt-parent = <&gic>;
845 };
846 };
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