1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2016-2018 Toradex AG
4 */
5
6 #include "tegra124.dtsi"
7 #include "tegra124-apalis-emc.dtsi"
8
9 /*
10 * Toradex Apalis TK1 Module Device Tree
11 * Compatible for Revisions 2GB: V1.2A
12 */
13 / {
14 memory@80000000 {
15 reg = <0x0 0x80000000 0x0 0x80000000>;
16 };
17
18 pcie@1003000 {
19 status = "okay";
20
21 avddio-pex-supply = <®_1v05_vdd>;
22 avdd-pex-pll-supply = <®_1v05_vdd>;
23 avdd-pll-erefe-supply = <®_1v05_avdd>;
24 dvddio-pex-supply = <®_1v05_vdd>;
25 hvdd-pex-pll-e-supply = <®_module_3v3>;
26 hvdd-pex-supply = <®_module_3v3>;
27 vddio-pex-ctl-supply = <®_module_3v3>;
28
29 /* Apalis PCIe (additional lane Apalis type specific) */
30 pci@1,0 {
31 /* PCIE1_RX/TX and TS_DIFF1/2 */
32 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
33 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
34 phy-names = "pcie-0", "pcie-1";
35 };
36
37 /* I210 Gigabit Ethernet Controller (On-module) */
38 pci@2,0 {
39 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
40 phy-names = "pcie-0";
41 status = "okay";
42
43 ethernet@0,0 {
44 reg = <0 0 0 0 0>;
45 local-mac-address = [00 00 00 00 00 00];
46 };
47 };
48 };
49
50 host1x@50000000 {
51 hdmi@54280000 {
52 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
53 nvidia,hpd-gpio =
54 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
55 pll-supply = <®_1v05_avdd_hdmi_pll>;
56 vdd-supply = <®_3v3_avdd_hdmi>;
57 };
58 };
59
60 gpu@57000000 {
61 /*
62 * Node left disabled on purpose - the bootloader will enable
63 * it after having set the VPR up
64 */
65 vdd-supply = <®_vdd_gpu>;
66 };
67
68 gpio@6000d000 {
69 /* I210 Gigabit Ethernet Controller Reset */
70 lan-reset-n-hog {
71 gpio-hog;
72 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
73 output-high;
74 line-name = "LAN_RESET_N";
75 };
76
77 /* Control MXM3 pin 26 Reset Module Output Carrier Input */
78 reset-moci-ctrl-hog {
79 gpio-hog;
80 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
81 output-high;
82 line-name = "RESET_MOCI_CTRL";
83 };
84 };
85
86 pinmux@70000868 {
87 pinctrl-names = "default";
88 pinctrl-0 = <&state_default>;
89
90 state_default: pinmux {
91 /* Analogue Audio (On-module) */
92 dap3-fs-pp0 {
93 nvidia,pins = "dap3_fs_pp0";
94 nvidia,function = "i2s2";
95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <TEGRA_PIN_DISABLE>;
97 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
98 };
99 dap3-din-pp1 {
100 nvidia,pins = "dap3_din_pp1";
101 nvidia,function = "i2s2";
102 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103 nvidia,tristate = <TEGRA_PIN_ENABLE>;
104 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
105 };
106 dap3-dout-pp2 {
107 nvidia,pins = "dap3_dout_pp2";
108 nvidia,function = "i2s2";
109 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
110 nvidia,tristate = <TEGRA_PIN_DISABLE>;
111 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
112 };
113 dap3-sclk-pp3 {
114 nvidia,pins = "dap3_sclk_pp3";
115 nvidia,function = "i2s2";
116 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
118 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
119 };
120 dap-mclk1-pw4 {
121 nvidia,pins = "dap_mclk1_pw4";
122 nvidia,function = "extperiph1";
123 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
125 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
126 };
127
128 /* Apalis BKL1_ON */
129 pbb5 {
130 nvidia,pins = "pbb5";
131 nvidia,function = "vgp5";
132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
134 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
135 };
136
137 /* Apalis BKL1_PWM */
138 pu6 {
139 nvidia,pins = "pu6";
140 nvidia,function = "pwm3";
141 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
142 nvidia,tristate = <TEGRA_PIN_DISABLE>;
143 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
144 };
145
146 /* Apalis CAM1_MCLK */
147 cam-mclk-pcc0 {
148 nvidia,pins = "cam_mclk_pcc0";
149 nvidia,function = "vi_alt3";
150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
152 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
153 };
154
155 /* Apalis Digital Audio */
156 dap2-fs-pa2 {
157 nvidia,pins = "dap2_fs_pa2";
158 nvidia,function = "hda";
159 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
160 nvidia,tristate = <TEGRA_PIN_DISABLE>;
161 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
162 };
163 dap2-sclk-pa3 {
164 nvidia,pins = "dap2_sclk_pa3";
165 nvidia,function = "hda";
166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristate = <TEGRA_PIN_DISABLE>;
168 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
169 };
170 dap2-din-pa4 {
171 nvidia,pins = "dap2_din_pa4";
172 nvidia,function = "hda";
173 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
174 nvidia,tristate = <TEGRA_PIN_ENABLE>;
175 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
176 };
177 dap2-dout-pa5 {
178 nvidia,pins = "dap2_dout_pa5";
179 nvidia,function = "hda";
180 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
181 nvidia,tristate = <TEGRA_PIN_DISABLE>;
182 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
183 };
184 pbb3 { /* DAP1_RESET */
185 nvidia,pins = "pbb3";
186 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187 nvidia,tristate = <TEGRA_PIN_DISABLE>;
188 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
189 };
190 clk3-out-pee0 {
191 nvidia,pins = "clk3_out_pee0";
192 nvidia,function = "extperiph3";
193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
195 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
196 };
197
198 /* Apalis GPIO */
199 usb-vbus-en0-pn4 {
200 nvidia,pins = "usb_vbus_en0_pn4";
201 nvidia,function = "rsvd2";
202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
204 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
205 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
206 };
207 usb-vbus-en1-pn5 {
208 nvidia,pins = "usb_vbus_en1_pn5";
209 nvidia,function = "rsvd2";
210 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
211 nvidia,tristate = <TEGRA_PIN_DISABLE>;
212 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
213 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
214 };
215 pex-l0-rst-n-pdd1 {
216 nvidia,pins = "pex_l0_rst_n_pdd1";
217 nvidia,function = "rsvd2";
218 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
219 nvidia,tristate = <TEGRA_PIN_DISABLE>;
220 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
221 };
222 pex-l0-clkreq-n-pdd2 {
223 nvidia,pins = "pex_l0_clkreq_n_pdd2";
224 nvidia,function = "rsvd2";
225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
227 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228 };
229 pex-l1-rst-n-pdd5 {
230 nvidia,pins = "pex_l1_rst_n_pdd5";
231 nvidia,function = "rsvd2";
232 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
233 nvidia,tristate = <TEGRA_PIN_DISABLE>;
234 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
235 };
236 pex-l1-clkreq-n-pdd6 {
237 nvidia,pins = "pex_l1_clkreq_n_pdd6";
238 nvidia,function = "rsvd2";
239 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
240 nvidia,tristate = <TEGRA_PIN_DISABLE>;
241 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
242 };
243 dp-hpd-pff0 {
244 nvidia,pins = "dp_hpd_pff0";
245 nvidia,function = "dp";
246 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
247 nvidia,tristate = <TEGRA_PIN_DISABLE>;
248 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
249 };
250 pff2 {
251 nvidia,pins = "pff2";
252 nvidia,function = "rsvd2";
253 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
254 nvidia,tristate = <TEGRA_PIN_DISABLE>;
255 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
256 };
257 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
258 nvidia,pins = "owr";
259 nvidia,function = "rsvd2";
260 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
261 nvidia,tristate = <TEGRA_PIN_ENABLE>;
262 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
263 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
264 };
265
266 /* Apalis HDMI1_CEC */
267 hdmi-cec-pee3 {
268 nvidia,pins = "hdmi_cec_pee3";
269 nvidia,function = "cec";
270 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
271 nvidia,tristate = <TEGRA_PIN_DISABLE>;
272 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
273 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
274 };
275
276 /* Apalis HDMI1_HPD */
277 hdmi-int-pn7 {
278 nvidia,pins = "hdmi_int_pn7";
279 nvidia,function = "rsvd1";
280 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
281 nvidia,tristate = <TEGRA_PIN_ENABLE>;
282 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
283 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
284 };
285
286 /* Apalis I2C1 */
287 gen1-i2c-scl-pc4 {
288 nvidia,pins = "gen1_i2c_scl_pc4";
289 nvidia,function = "i2c1";
290 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
291 nvidia,tristate = <TEGRA_PIN_DISABLE>;
292 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
293 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
294 };
295 gen1-i2c-sda-pc5 {
296 nvidia,pins = "gen1_i2c_sda_pc5";
297 nvidia,function = "i2c1";
298 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
299 nvidia,tristate = <TEGRA_PIN_DISABLE>;
300 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
301 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
302 };
303
304 /* Apalis I2C3 (CAM) */
305 cam-i2c-scl-pbb1 {
306 nvidia,pins = "cam_i2c_scl_pbb1";
307 nvidia,function = "i2c3";
308 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
309 nvidia,tristate = <TEGRA_PIN_DISABLE>;
310 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
311 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
312 };
313 cam-i2c-sda-pbb2 {
314 nvidia,pins = "cam_i2c_sda_pbb2";
315 nvidia,function = "i2c3";
316 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
317 nvidia,tristate = <TEGRA_PIN_DISABLE>;
318 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
319 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
320 };
321
322 /* Apalis I2C4 (DDC) */
323 ddc-scl-pv4 {
324 nvidia,pins = "ddc_scl_pv4";
325 nvidia,function = "i2c4";
326 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
327 nvidia,tristate = <TEGRA_PIN_DISABLE>;
328 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
329 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
330 };
331 ddc-sda-pv5 {
332 nvidia,pins = "ddc_sda_pv5";
333 nvidia,function = "i2c4";
334 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
335 nvidia,tristate = <TEGRA_PIN_DISABLE>;
336 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
337 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
338 };
339
340 /* Apalis MMC1 */
341 sdmmc1-cd-n-pv3 { /* CD# GPIO */
342 nvidia,pins = "sdmmc1_wp_n_pv3";
343 nvidia,function = "sdmmc1";
344 nvidia,pull = <TEGRA_PIN_PULL_UP>;
345 nvidia,tristate = <TEGRA_PIN_ENABLE>;
346 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
347 };
348 clk2-out-pw5 { /* D5 GPIO */
349 nvidia,pins = "clk2_out_pw5";
350 nvidia,function = "rsvd2";
351 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
352 nvidia,tristate = <TEGRA_PIN_DISABLE>;
353 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
354 };
355 sdmmc1-dat3-py4 {
356 nvidia,pins = "sdmmc1_dat3_py4";
357 nvidia,function = "sdmmc1";
358 nvidia,pull = <TEGRA_PIN_PULL_UP>;
359 nvidia,tristate = <TEGRA_PIN_DISABLE>;
360 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
361 };
362 sdmmc1-dat2-py5 {
363 nvidia,pins = "sdmmc1_dat2_py5";
364 nvidia,function = "sdmmc1";
365 nvidia,pull = <TEGRA_PIN_PULL_UP>;
366 nvidia,tristate = <TEGRA_PIN_DISABLE>;
367 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
368 };
369 sdmmc1-dat1-py6 {
370 nvidia,pins = "sdmmc1_dat1_py6";
371 nvidia,function = "sdmmc1";
372 nvidia,pull = <TEGRA_PIN_PULL_UP>;
373 nvidia,tristate = <TEGRA_PIN_DISABLE>;
374 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
375 };
376 sdmmc1-dat0-py7 {
377 nvidia,pins = "sdmmc1_dat0_py7";
378 nvidia,function = "sdmmc1";
379 nvidia,pull = <TEGRA_PIN_PULL_UP>;
380 nvidia,tristate = <TEGRA_PIN_DISABLE>;
381 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
382 };
383 sdmmc1-clk-pz0 {
384 nvidia,pins = "sdmmc1_clk_pz0";
385 nvidia,function = "sdmmc1";
386 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
387 nvidia,tristate = <TEGRA_PIN_DISABLE>;
388 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
389 };
390 sdmmc1-cmd-pz1 {
391 nvidia,pins = "sdmmc1_cmd_pz1";
392 nvidia,function = "sdmmc1";
393 nvidia,pull = <TEGRA_PIN_PULL_UP>;
394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
395 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
396 };
397 clk2-req-pcc5 { /* D4 GPIO */
398 nvidia,pins = "clk2_req_pcc5";
399 nvidia,function = "rsvd2";
400 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
401 nvidia,tristate = <TEGRA_PIN_DISABLE>;
402 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
403 };
404 sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
405 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
406 nvidia,function = "rsvd2";
407 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
408 nvidia,tristate = <TEGRA_PIN_DISABLE>;
409 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
410 };
411 usb-vbus-en2-pff1 { /* D7 GPIO */
412 nvidia,pins = "usb_vbus_en2_pff1";
413 nvidia,function = "rsvd2";
414 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
415 nvidia,tristate = <TEGRA_PIN_DISABLE>;
416 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
417 };
418
419 /* Apalis PWM */
420 ph0 {
421 nvidia,pins = "ph0";
422 nvidia,function = "pwm0";
423 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
424 nvidia,tristate = <TEGRA_PIN_DISABLE>;
425 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
426 };
427 ph1 {
428 nvidia,pins = "ph1";
429 nvidia,function = "pwm1";
430 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
431 nvidia,tristate = <TEGRA_PIN_DISABLE>;
432 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
433 };
434 ph2 {
435 nvidia,pins = "ph2";
436 nvidia,function = "pwm2";
437 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
438 nvidia,tristate = <TEGRA_PIN_DISABLE>;
439 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
440 };
441 /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
442 ph3 {
443 nvidia,pins = "ph3";
444 nvidia,function = "pwm3";
445 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
446 nvidia,tristate = <TEGRA_PIN_DISABLE>;
447 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
448 };
449
450 /* Apalis SATA1_ACT# */
451 dap1-dout-pn2 {
452 nvidia,pins = "dap1_dout_pn2";
453 nvidia,function = "gmi";
454 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
455 nvidia,tristate = <TEGRA_PIN_DISABLE>;
456 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
457 };
458
459 /* Apalis SD1 */
460 sdmmc3-clk-pa6 {
461 nvidia,pins = "sdmmc3_clk_pa6";
462 nvidia,function = "sdmmc3";
463 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
464 nvidia,tristate = <TEGRA_PIN_DISABLE>;
465 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
466 };
467 sdmmc3-cmd-pa7 {
468 nvidia,pins = "sdmmc3_cmd_pa7";
469 nvidia,function = "sdmmc3";
470 nvidia,pull = <TEGRA_PIN_PULL_UP>;
471 nvidia,tristate = <TEGRA_PIN_DISABLE>;
472 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
473 };
474 sdmmc3-dat3-pb4 {
475 nvidia,pins = "sdmmc3_dat3_pb4";
476 nvidia,function = "sdmmc3";
477 nvidia,pull = <TEGRA_PIN_PULL_UP>;
478 nvidia,tristate = <TEGRA_PIN_DISABLE>;
479 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
480 };
481 sdmmc3-dat2-pb5 {
482 nvidia,pins = "sdmmc3_dat2_pb5";
483 nvidia,function = "sdmmc3";
484 nvidia,pull = <TEGRA_PIN_PULL_UP>;
485 nvidia,tristate = <TEGRA_PIN_DISABLE>;
486 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
487 };
488 sdmmc3-dat1-pb6 {
489 nvidia,pins = "sdmmc3_dat1_pb6";
490 nvidia,function = "sdmmc3";
491 nvidia,pull = <TEGRA_PIN_PULL_UP>;
492 nvidia,tristate = <TEGRA_PIN_DISABLE>;
493 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
494 };
495 sdmmc3-dat0-pb7 {
496 nvidia,pins = "sdmmc3_dat0_pb7";
497 nvidia,function = "sdmmc3";
498 nvidia,pull = <TEGRA_PIN_PULL_UP>;
499 nvidia,tristate = <TEGRA_PIN_DISABLE>;
500 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
501 };
502 sdmmc3-cd-n-pv2 { /* CD# GPIO */
503 nvidia,pins = "sdmmc3_cd_n_pv2";
504 nvidia,function = "rsvd3";
505 nvidia,pull = <TEGRA_PIN_PULL_UP>;
506 nvidia,tristate = <TEGRA_PIN_ENABLE>;
507 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
508 };
509
510 /* Apalis SPDIF */
511 spdif-out-pk5 {
512 nvidia,pins = "spdif_out_pk5";
513 nvidia,function = "spdif";
514 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
515 nvidia,tristate = <TEGRA_PIN_DISABLE>;
516 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
517 };
518 spdif-in-pk6 {
519 nvidia,pins = "spdif_in_pk6";
520 nvidia,function = "spdif";
521 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
522 nvidia,tristate = <TEGRA_PIN_ENABLE>;
523 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
524 };
525
526 /* Apalis SPI1 */
527 ulpi-clk-py0 {
528 nvidia,pins = "ulpi_clk_py0";
529 nvidia,function = "spi1";
530 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531 nvidia,tristate = <TEGRA_PIN_DISABLE>;
532 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
533 };
534 ulpi-dir-py1 {
535 nvidia,pins = "ulpi_dir_py1";
536 nvidia,function = "spi1";
537 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
538 nvidia,tristate = <TEGRA_PIN_ENABLE>;
539 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
540 };
541 ulpi-nxt-py2 {
542 nvidia,pins = "ulpi_nxt_py2";
543 nvidia,function = "spi1";
544 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
545 nvidia,tristate = <TEGRA_PIN_DISABLE>;
546 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
547 };
548 ulpi-stp-py3 {
549 nvidia,pins = "ulpi_stp_py3";
550 nvidia,function = "spi1";
551 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
552 nvidia,tristate = <TEGRA_PIN_DISABLE>;
553 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
554 };
555
556 /* Apalis SPI2 */
557 pg5 {
558 nvidia,pins = "pg5";
559 nvidia,function = "spi4";
560 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
561 nvidia,tristate = <TEGRA_PIN_DISABLE>;
562 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
563 };
564 pg6 {
565 nvidia,pins = "pg6";
566 nvidia,function = "spi4";
567 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
568 nvidia,tristate = <TEGRA_PIN_DISABLE>;
569 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
570 };
571 pg7 {
572 nvidia,pins = "pg7";
573 nvidia,function = "spi4";
574 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
575 nvidia,tristate = <TEGRA_PIN_ENABLE>;
576 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
577 };
578 pi3 {
579 nvidia,pins = "pi3";
580 nvidia,function = "spi4";
581 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
582 nvidia,tristate = <TEGRA_PIN_DISABLE>;
583 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
584 };
585
586 /* Apalis UART1 */
587 pb1 { /* DCD GPIO */
588 nvidia,pins = "pb1";
589 nvidia,function = "rsvd2";
590 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
591 nvidia,tristate = <TEGRA_PIN_ENABLE>;
592 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
593 };
594 pk7 { /* RI GPIO */
595 nvidia,pins = "pk7";
596 nvidia,function = "rsvd2";
597 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598 nvidia,tristate = <TEGRA_PIN_ENABLE>;
599 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600 };
601 uart1-txd-pu0 {
602 nvidia,pins = "pu0";
603 nvidia,function = "uarta";
604 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
605 nvidia,tristate = <TEGRA_PIN_DISABLE>;
606 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
607 };
608 uart1-rxd-pu1 {
609 nvidia,pins = "pu1";
610 nvidia,function = "uarta";
611 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
612 nvidia,tristate = <TEGRA_PIN_ENABLE>;
613 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
614 };
615 uart1-cts-n-pu2 {
616 nvidia,pins = "pu2";
617 nvidia,function = "uarta";
618 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
619 nvidia,tristate = <TEGRA_PIN_ENABLE>;
620 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
621 };
622 uart1-rts-n-pu3 {
623 nvidia,pins = "pu3";
624 nvidia,function = "uarta";
625 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
626 nvidia,tristate = <TEGRA_PIN_DISABLE>;
627 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
628 };
629 uart3-cts-n-pa1 { /* DSR GPIO */
630 nvidia,pins = "uart3_cts_n_pa1";
631 nvidia,function = "gmi";
632 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
633 nvidia,tristate = <TEGRA_PIN_ENABLE>;
634 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
635 };
636 uart3-rts-n-pc0 { /* DTR GPIO */
637 nvidia,pins = "uart3_rts_n_pc0";
638 nvidia,function = "gmi";
639 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
640 nvidia,tristate = <TEGRA_PIN_DISABLE>;
641 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
642 };
643
644 /* Apalis UART2 */
645 uart2-txd-pc2 {
646 nvidia,pins = "uart2_txd_pc2";
647 nvidia,function = "irda";
648 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
649 nvidia,tristate = <TEGRA_PIN_DISABLE>;
650 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
651 };
652 uart2-rxd-pc3 {
653 nvidia,pins = "uart2_rxd_pc3";
654 nvidia,function = "irda";
655 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
656 nvidia,tristate = <TEGRA_PIN_ENABLE>;
657 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
658 };
659 uart2-cts-n-pj5 {
660 nvidia,pins = "uart2_cts_n_pj5";
661 nvidia,function = "uartb";
662 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
663 nvidia,tristate = <TEGRA_PIN_ENABLE>;
664 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
665 };
666 uart2-rts-n-pj6 {
667 nvidia,pins = "uart2_rts_n_pj6";
668 nvidia,function = "uartb";
669 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
670 nvidia,tristate = <TEGRA_PIN_DISABLE>;
671 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
672 };
673
674 /* Apalis UART3 */
675 uart3-txd-pw6 {
676 nvidia,pins = "uart3_txd_pw6";
677 nvidia,function = "uartc";
678 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
679 nvidia,tristate = <TEGRA_PIN_DISABLE>;
680 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
681 };
682 uart3-rxd-pw7 {
683 nvidia,pins = "uart3_rxd_pw7";
684 nvidia,function = "uartc";
685 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
686 nvidia,tristate = <TEGRA_PIN_ENABLE>;
687 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
688 };
689
690 /* Apalis UART4 */
691 uart4-rxd-pb0 {
692 nvidia,pins = "pb0";
693 nvidia,function = "uartd";
694 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
695 nvidia,tristate = <TEGRA_PIN_ENABLE>;
696 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
697 };
698 uart4-txd-pj7 {
699 nvidia,pins = "pj7";
700 nvidia,function = "uartd";
701 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
702 nvidia,tristate = <TEGRA_PIN_DISABLE>;
703 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
704 };
705
706 /* Apalis USBH_EN */
707 gen2-i2c-sda-pt6 {
708 nvidia,pins = "gen2_i2c_sda_pt6";
709 nvidia,function = "rsvd2";
710 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
711 nvidia,tristate = <TEGRA_PIN_DISABLE>;
712 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
713 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
714 };
715
716 /* Apalis USBH_OC# */
717 pbb0 {
718 nvidia,pins = "pbb0";
719 nvidia,function = "vgp6";
720 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
721 nvidia,tristate = <TEGRA_PIN_ENABLE>;
722 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
723 };
724
725 /* Apalis USBO1_EN */
726 gen2-i2c-scl-pt5 {
727 nvidia,pins = "gen2_i2c_scl_pt5";
728 nvidia,function = "rsvd2";
729 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
730 nvidia,tristate = <TEGRA_PIN_DISABLE>;
731 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
732 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
733 };
734
735 /* Apalis USBO1_OC# */
736 pbb4 {
737 nvidia,pins = "pbb4";
738 nvidia,function = "vgp4";
739 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
740 nvidia,tristate = <TEGRA_PIN_ENABLE>;
741 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
742 };
743
744 /* Apalis WAKE1_MICO */
745 pex-wake-n-pdd3 {
746 nvidia,pins = "pex_wake_n_pdd3";
747 nvidia,function = "rsvd2";
748 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
749 nvidia,tristate = <TEGRA_PIN_ENABLE>;
750 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
751 };
752
753 /* CORE_PWR_REQ */
754 core-pwr-req {
755 nvidia,pins = "core_pwr_req";
756 nvidia,function = "pwron";
757 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
758 nvidia,tristate = <TEGRA_PIN_DISABLE>;
759 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
760 };
761
762 /* CPU_PWR_REQ */
763 cpu-pwr-req {
764 nvidia,pins = "cpu_pwr_req";
765 nvidia,function = "cpu";
766 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
767 nvidia,tristate = <TEGRA_PIN_DISABLE>;
768 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
769 };
770
771 /* DVFS */
772 dvfs-pwm-px0 {
773 nvidia,pins = "dvfs_pwm_px0";
774 nvidia,function = "cldvfs";
775 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
776 nvidia,tristate = <TEGRA_PIN_DISABLE>;
777 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
778 };
779 dvfs-clk-px2 {
780 nvidia,pins = "dvfs_clk_px2";
781 nvidia,function = "cldvfs";
782 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
783 nvidia,tristate = <TEGRA_PIN_DISABLE>;
784 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
785 };
786
787 /* eMMC */
788 sdmmc4-dat0-paa0 {
789 nvidia,pins = "sdmmc4_dat0_paa0";
790 nvidia,function = "sdmmc4";
791 nvidia,pull = <TEGRA_PIN_PULL_UP>;
792 nvidia,tristate = <TEGRA_PIN_DISABLE>;
793 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
794 };
795 sdmmc4-dat1-paa1 {
796 nvidia,pins = "sdmmc4_dat1_paa1";
797 nvidia,function = "sdmmc4";
798 nvidia,pull = <TEGRA_PIN_PULL_UP>;
799 nvidia,tristate = <TEGRA_PIN_DISABLE>;
800 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
801 };
802 sdmmc4-dat2-paa2 {
803 nvidia,pins = "sdmmc4_dat2_paa2";
804 nvidia,function = "sdmmc4";
805 nvidia,pull = <TEGRA_PIN_PULL_UP>;
806 nvidia,tristate = <TEGRA_PIN_DISABLE>;
807 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
808 };
809 sdmmc4-dat3-paa3 {
810 nvidia,pins = "sdmmc4_dat3_paa3";
811 nvidia,function = "sdmmc4";
812 nvidia,pull = <TEGRA_PIN_PULL_UP>;
813 nvidia,tristate = <TEGRA_PIN_DISABLE>;
814 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815 };
816 sdmmc4-dat4-paa4 {
817 nvidia,pins = "sdmmc4_dat4_paa4";
818 nvidia,function = "sdmmc4";
819 nvidia,pull = <TEGRA_PIN_PULL_UP>;
820 nvidia,tristate = <TEGRA_PIN_DISABLE>;
821 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
822 };
823 sdmmc4-dat5-paa5 {
824 nvidia,pins = "sdmmc4_dat5_paa5";
825 nvidia,function = "sdmmc4";
826 nvidia,pull = <TEGRA_PIN_PULL_UP>;
827 nvidia,tristate = <TEGRA_PIN_DISABLE>;
828 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
829 };
830 sdmmc4-dat6-paa6 {
831 nvidia,pins = "sdmmc4_dat6_paa6";
832 nvidia,function = "sdmmc4";
833 nvidia,pull = <TEGRA_PIN_PULL_UP>;
834 nvidia,tristate = <TEGRA_PIN_DISABLE>;
835 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
836 };
837 sdmmc4-dat7-paa7 {
838 nvidia,pins = "sdmmc4_dat7_paa7";
839 nvidia,function = "sdmmc4";
840 nvidia,pull = <TEGRA_PIN_PULL_UP>;
841 nvidia,tristate = <TEGRA_PIN_DISABLE>;
842 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
843 };
844 sdmmc4-clk-pcc4 {
845 nvidia,pins = "sdmmc4_clk_pcc4";
846 nvidia,function = "sdmmc4";
847 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
848 nvidia,tristate = <TEGRA_PIN_DISABLE>;
849 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
850 };
851 sdmmc4-cmd-pt7 {
852 nvidia,pins = "sdmmc4_cmd_pt7";
853 nvidia,function = "sdmmc4";
854 nvidia,pull = <TEGRA_PIN_PULL_UP>;
855 nvidia,tristate = <TEGRA_PIN_DISABLE>;
856 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
857 };
858
859 /* JTAG_RTCK */
860 jtag-rtck {
861 nvidia,pins = "jtag_rtck";
862 nvidia,function = "rtck";
863 nvidia,pull = <TEGRA_PIN_PULL_UP>;
864 nvidia,tristate = <TEGRA_PIN_DISABLE>;
865 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
866 };
867
868 /* LAN_DEV_OFF# */
869 ulpi-data5-po6 {
870 nvidia,pins = "ulpi_data5_po6";
871 nvidia,function = "ulpi";
872 nvidia,pull = <TEGRA_PIN_PULL_UP>;
873 nvidia,tristate = <TEGRA_PIN_DISABLE>;
874 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
875 };
876
877 /* LAN_RESET# */
878 kb-row10-ps2 {
879 nvidia,pins = "kb_row10_ps2";
880 nvidia,function = "rsvd2";
881 nvidia,pull = <TEGRA_PIN_PULL_UP>;
882 nvidia,tristate = <TEGRA_PIN_DISABLE>;
883 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
884 };
885
886 /* LAN_WAKE# */
887 ulpi-data4-po5 {
888 nvidia,pins = "ulpi_data4_po5";
889 nvidia,function = "ulpi";
890 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
891 nvidia,tristate = <TEGRA_PIN_ENABLE>;
892 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
893 };
894
895 /* MCU_INT1# */
896 pk2 {
897 nvidia,pins = "pk2";
898 nvidia,function = "rsvd1";
899 nvidia,pull = <TEGRA_PIN_PULL_UP>;
900 nvidia,tristate = <TEGRA_PIN_ENABLE>;
901 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
902 };
903
904 /* MCU_INT2# */
905 pj2 {
906 nvidia,pins = "pj2";
907 nvidia,function = "rsvd1";
908 nvidia,pull = <TEGRA_PIN_PULL_UP>;
909 nvidia,tristate = <TEGRA_PIN_ENABLE>;
910 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
911 };
912
913 /* MCU_INT3# */
914 pi5 {
915 nvidia,pins = "pi5";
916 nvidia,function = "rsvd2";
917 nvidia,pull = <TEGRA_PIN_PULL_UP>;
918 nvidia,tristate = <TEGRA_PIN_ENABLE>;
919 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
920 };
921
922 /* MCU_INT4# */
923 pj0 {
924 nvidia,pins = "pj0";
925 nvidia,function = "rsvd1";
926 nvidia,pull = <TEGRA_PIN_PULL_UP>;
927 nvidia,tristate = <TEGRA_PIN_ENABLE>;
928 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
929 };
930
931 /* MCU_RESET */
932 pbb6 {
933 nvidia,pins = "pbb6";
934 nvidia,function = "rsvd2";
935 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
936 nvidia,tristate = <TEGRA_PIN_DISABLE>;
937 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
938 };
939
940 /* MCU SPI */
941 gpio-x4-aud-px4 {
942 nvidia,pins = "gpio_x4_aud_px4";
943 nvidia,function = "spi2";
944 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
945 nvidia,tristate = <TEGRA_PIN_DISABLE>;
946 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
947 };
948 gpio-x5-aud-px5 {
949 nvidia,pins = "gpio_x5_aud_px5";
950 nvidia,function = "spi2";
951 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
952 nvidia,tristate = <TEGRA_PIN_DISABLE>;
953 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
954 };
955 gpio-x6-aud-px6 { /* MCU_CS */
956 nvidia,pins = "gpio_x6_aud_px6";
957 nvidia,function = "spi2";
958 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
959 nvidia,tristate = <TEGRA_PIN_DISABLE>;
960 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
961 };
962 gpio-x7-aud-px7 {
963 nvidia,pins = "gpio_x7_aud_px7";
964 nvidia,function = "spi2";
965 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
966 nvidia,tristate = <TEGRA_PIN_ENABLE>;
967 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
968 };
969 gpio-w2-aud-pw2 { /* MCU_CSEZP */
970 nvidia,pins = "gpio_w2_aud_pw2";
971 nvidia,function = "spi2";
972 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
973 nvidia,tristate = <TEGRA_PIN_DISABLE>;
974 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
975 };
976
977 /* PMIC_CLK_32K */
978 clk-32k-in {
979 nvidia,pins = "clk_32k_in";
980 nvidia,function = "clk";
981 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
982 nvidia,tristate = <TEGRA_PIN_ENABLE>;
983 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
984 };
985
986 /* PMIC_CPU_OC_INT */
987 clk-32k-out-pa0 {
988 nvidia,pins = "clk_32k_out_pa0";
989 nvidia,function = "soc";
990 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
991 nvidia,tristate = <TEGRA_PIN_ENABLE>;
992 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
993 };
994
995 /* PWR_I2C */
996 pwr-i2c-scl-pz6 {
997 nvidia,pins = "pwr_i2c_scl_pz6";
998 nvidia,function = "i2cpwr";
999 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1000 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1001 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1002 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1003 };
1004 pwr-i2c-sda-pz7 {
1005 nvidia,pins = "pwr_i2c_sda_pz7";
1006 nvidia,function = "i2cpwr";
1007 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1008 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1009 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1010 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1011 };
1012
1013 /* PWR_INT_N */
1014 pwr-int-n {
1015 nvidia,pins = "pwr_int_n";
1016 nvidia,function = "pmi";
1017 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1018 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1019 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1020 };
1021
1022 /* RESET_MOCI_CTRL */
1023 pu4 {
1024 nvidia,pins = "pu4";
1025 nvidia,function = "gmi";
1026 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1027 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1028 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1029 };
1030
1031 /* RESET_OUT_N */
1032 reset-out-n {
1033 nvidia,pins = "reset_out_n";
1034 nvidia,function = "reset_out_n";
1035 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1036 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1037 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1038 };
1039
1040 /* SHIFT_CTRL_DIR_IN */
1041 kb-row0-pr0 {
1042 nvidia,pins = "kb_row0_pr0";
1043 nvidia,function = "rsvd2";
1044 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1045 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1046 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1047 };
1048 kb-row1-pr1 {
1049 nvidia,pins = "kb_row1_pr1";
1050 nvidia,function = "rsvd2";
1051 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1052 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1053 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1054 };
1055
1056 /* Configure level-shifter as output for HDA */
1057 kb-row11-ps3 {
1058 nvidia,pins = "kb_row11_ps3";
1059 nvidia,function = "rsvd2";
1060 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1061 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1062 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1063 };
1064
1065 /* SHIFT_CTRL_DIR_OUT */
1066 kb-col5-pq5 {
1067 nvidia,pins = "kb_col5_pq5";
1068 nvidia,function = "rsvd2";
1069 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1070 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1071 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1072 };
1073 kb-col6-pq6 {
1074 nvidia,pins = "kb_col6_pq6";
1075 nvidia,function = "rsvd2";
1076 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1077 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1078 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1079 };
1080 kb-col7-pq7 {
1081 nvidia,pins = "kb_col7_pq7";
1082 nvidia,function = "rsvd2";
1083 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1084 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1085 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1086 };
1087
1088 /* SHIFT_CTRL_OE */
1089 kb-col0-pq0 {
1090 nvidia,pins = "kb_col0_pq0";
1091 nvidia,function = "rsvd2";
1092 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1093 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1094 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1095 };
1096 kb-col1-pq1 {
1097 nvidia,pins = "kb_col1_pq1";
1098 nvidia,function = "rsvd2";
1099 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1100 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1101 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1102 };
1103 kb-col2-pq2 {
1104 nvidia,pins = "kb_col2_pq2";
1105 nvidia,function = "rsvd2";
1106 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1107 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1108 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1109 };
1110 kb-col4-pq4 {
1111 nvidia,pins = "kb_col4_pq4";
1112 nvidia,function = "kbc";
1113 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1114 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1115 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1116 };
1117 kb-row2-pr2 {
1118 nvidia,pins = "kb_row2_pr2";
1119 nvidia,function = "rsvd2";
1120 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1121 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1122 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1123 };
1124
1125 /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
1126 pi6 {
1127 nvidia,pins = "pi6";
1128 nvidia,function = "rsvd1";
1129 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1130 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1131 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1132 };
1133
1134 /* TOUCH_INT */
1135 gpio-w3-aud-pw3 {
1136 nvidia,pins = "gpio_w3_aud_pw3";
1137 nvidia,function = "spi6";
1138 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1139 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1140 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1141 };
1142
1143 pc7 { /* NC */
1144 nvidia,pins = "pc7";
1145 nvidia,function = "rsvd1";
1146 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1147 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1148 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1149 };
1150 pg0 { /* NC */
1151 nvidia,pins = "pg0";
1152 nvidia,function = "rsvd1";
1153 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1154 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1155 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1156 };
1157 pg1 { /* NC */
1158 nvidia,pins = "pg1";
1159 nvidia,function = "rsvd1";
1160 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1161 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1162 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1163 };
1164 pg2 { /* NC */
1165 nvidia,pins = "pg2";
1166 nvidia,function = "rsvd1";
1167 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1168 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1169 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1170 };
1171 pg3 { /* NC */
1172 nvidia,pins = "pg3";
1173 nvidia,function = "rsvd1";
1174 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1175 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1176 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1177 };
1178 pg4 { /* NC */
1179 nvidia,pins = "pg4";
1180 nvidia,function = "rsvd1";
1181 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1182 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1183 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1184 };
1185 ph4 { /* NC */
1186 nvidia,pins = "ph4";
1187 nvidia,function = "rsvd2";
1188 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1189 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1190 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1191 };
1192 ph5 { /* NC */
1193 nvidia,pins = "ph5";
1194 nvidia,function = "rsvd2";
1195 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1196 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1197 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1198 };
1199 ph6 { /* NC */
1200 nvidia,pins = "ph6";
1201 nvidia,function = "gmi";
1202 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1203 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1204 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1205 };
1206 ph7 { /* NC */
1207 nvidia,pins = "ph7";
1208 nvidia,function = "gmi";
1209 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1210 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1211 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1212 };
1213 pi0 { /* NC */
1214 nvidia,pins = "pi0";
1215 nvidia,function = "rsvd1";
1216 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1217 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1218 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1219 };
1220 pi1 { /* NC */
1221 nvidia,pins = "pi1";
1222 nvidia,function = "rsvd1";
1223 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1225 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1226 };
1227 pi2 { /* NC */
1228 nvidia,pins = "pi2";
1229 nvidia,function = "rsvd4";
1230 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1231 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1232 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1233 };
1234 pi4 { /* NC */
1235 nvidia,pins = "pi4";
1236 nvidia,function = "gmi";
1237 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1238 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1239 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1240 };
1241 pi7 { /* NC */
1242 nvidia,pins = "pi7";
1243 nvidia,function = "rsvd1";
1244 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1245 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1246 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1247 };
1248 pk0 { /* NC */
1249 nvidia,pins = "pk0";
1250 nvidia,function = "rsvd1";
1251 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1252 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1253 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1254 };
1255 pk1 { /* NC */
1256 nvidia,pins = "pk1";
1257 nvidia,function = "rsvd4";
1258 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1259 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1260 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1261 };
1262 pk3 { /* NC */
1263 nvidia,pins = "pk3";
1264 nvidia,function = "gmi";
1265 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1266 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1267 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1268 };
1269 pk4 { /* NC */
1270 nvidia,pins = "pk4";
1271 nvidia,function = "rsvd2";
1272 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1273 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1274 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1275 };
1276 dap1-fs-pn0 { /* NC */
1277 nvidia,pins = "dap1_fs_pn0";
1278 nvidia,function = "rsvd4";
1279 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1280 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1281 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1282 };
1283 dap1-din-pn1 { /* NC */
1284 nvidia,pins = "dap1_din_pn1";
1285 nvidia,function = "rsvd4";
1286 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1287 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1288 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1289 };
1290 dap1-sclk-pn3 { /* NC */
1291 nvidia,pins = "dap1_sclk_pn3";
1292 nvidia,function = "rsvd4";
1293 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1294 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1295 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1296 };
1297 ulpi-data7-po0 { /* NC */
1298 nvidia,pins = "ulpi_data7_po0";
1299 nvidia,function = "ulpi";
1300 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1301 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1302 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1303 };
1304 ulpi-data0-po1 { /* NC */
1305 nvidia,pins = "ulpi_data0_po1";
1306 nvidia,function = "ulpi";
1307 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1308 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1309 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1310 };
1311 ulpi-data1-po2 { /* NC */
1312 nvidia,pins = "ulpi_data1_po2";
1313 nvidia,function = "ulpi";
1314 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1315 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1316 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1317 };
1318 ulpi-data2-po3 { /* NC */
1319 nvidia,pins = "ulpi_data2_po3";
1320 nvidia,function = "ulpi";
1321 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1322 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1323 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1324 };
1325 ulpi-data3-po4 { /* NC */
1326 nvidia,pins = "ulpi_data3_po4";
1327 nvidia,function = "ulpi";
1328 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1329 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1330 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1331 };
1332 ulpi-data6-po7 { /* NC */
1333 nvidia,pins = "ulpi_data6_po7";
1334 nvidia,function = "ulpi";
1335 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1336 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1337 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1338 };
1339 dap4-fs-pp4 { /* NC */
1340 nvidia,pins = "dap4_fs_pp4";
1341 nvidia,function = "rsvd4";
1342 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1343 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1344 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1345 };
1346 dap4-din-pp5 { /* NC */
1347 nvidia,pins = "dap4_din_pp5";
1348 nvidia,function = "rsvd3";
1349 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1350 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1351 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1352 };
1353 dap4-dout-pp6 { /* NC */
1354 nvidia,pins = "dap4_dout_pp6";
1355 nvidia,function = "rsvd4";
1356 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1357 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1358 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1359 };
1360 dap4-sclk-pp7 { /* NC */
1361 nvidia,pins = "dap4_sclk_pp7";
1362 nvidia,function = "rsvd3";
1363 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1364 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1365 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1366 };
1367 kb-col3-pq3 { /* NC */
1368 nvidia,pins = "kb_col3_pq3";
1369 nvidia,function = "kbc";
1370 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1371 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1372 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1373 };
1374 kb-row3-pr3 { /* NC */
1375 nvidia,pins = "kb_row3_pr3";
1376 nvidia,function = "kbc";
1377 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1378 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1379 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1380 };
1381 kb-row4-pr4 { /* NC */
1382 nvidia,pins = "kb_row4_pr4";
1383 nvidia,function = "rsvd3";
1384 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1385 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1386 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1387 };
1388 kb-row5-pr5 { /* NC */
1389 nvidia,pins = "kb_row5_pr5";
1390 nvidia,function = "rsvd3";
1391 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1392 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1393 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1394 };
1395 kb-row6-pr6 { /* NC */
1396 nvidia,pins = "kb_row6_pr6";
1397 nvidia,function = "kbc";
1398 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1399 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1400 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1401 };
1402 kb-row7-pr7 { /* NC */
1403 nvidia,pins = "kb_row7_pr7";
1404 nvidia,function = "rsvd2";
1405 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1406 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1407 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1408 };
1409 kb-row8-ps0 { /* NC */
1410 nvidia,pins = "kb_row8_ps0";
1411 nvidia,function = "rsvd2";
1412 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1413 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1414 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1415 };
1416 kb-row9-ps1 { /* NC */
1417 nvidia,pins = "kb_row9_ps1";
1418 nvidia,function = "rsvd2";
1419 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1420 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1421 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1422 };
1423 kb-row12-ps4 { /* NC */
1424 nvidia,pins = "kb_row12_ps4";
1425 nvidia,function = "rsvd2";
1426 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1427 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1428 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1429 };
1430 kb-row13-ps5 { /* NC */
1431 nvidia,pins = "kb_row13_ps5";
1432 nvidia,function = "rsvd2";
1433 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1434 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1435 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1436 };
1437 kb-row14-ps6 { /* NC */
1438 nvidia,pins = "kb_row14_ps6";
1439 nvidia,function = "rsvd2";
1440 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1441 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1442 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1443 };
1444 kb-row15-ps7 { /* NC */
1445 nvidia,pins = "kb_row15_ps7";
1446 nvidia,function = "rsvd3";
1447 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1448 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1449 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1450 };
1451 kb-row16-pt0 { /* NC */
1452 nvidia,pins = "kb_row16_pt0";
1453 nvidia,function = "rsvd2";
1454 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1455 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1456 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1457 };
1458 kb-row17-pt1 { /* NC */
1459 nvidia,pins = "kb_row17_pt1";
1460 nvidia,function = "rsvd2";
1461 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1462 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1463 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1464 };
1465 pu5 { /* NC */
1466 nvidia,pins = "pu5";
1467 nvidia,function = "gmi";
1468 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1469 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1470 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1471 };
1472 /*
1473 * PCB Version Indication: V1.2 and later have GPIO_PV0
1474 * wired to GND, was NC before
1475 */
1476 pv0 {
1477 nvidia,pins = "pv0";
1478 nvidia,function = "rsvd1";
1479 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1480 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1481 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1482 };
1483 pv1 { /* NC */
1484 nvidia,pins = "pv1";
1485 nvidia,function = "rsvd1";
1486 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1487 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1488 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1489 };
1490 gpio-x1-aud-px1 { /* NC */
1491 nvidia,pins = "gpio_x1_aud_px1";
1492 nvidia,function = "rsvd2";
1493 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1494 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1495 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1496 };
1497 gpio-x3-aud-px3 { /* NC */
1498 nvidia,pins = "gpio_x3_aud_px3";
1499 nvidia,function = "rsvd4";
1500 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1501 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1502 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1503 };
1504 pbb7 { /* NC */
1505 nvidia,pins = "pbb7";
1506 nvidia,function = "rsvd2";
1507 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1508 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1509 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1510 };
1511 pcc1 { /* NC */
1512 nvidia,pins = "pcc1";
1513 nvidia,function = "rsvd2";
1514 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1515 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1516 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1517 };
1518 pcc2 { /* NC */
1519 nvidia,pins = "pcc2";
1520 nvidia,function = "rsvd2";
1521 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1522 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1523 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1524 };
1525 clk3-req-pee1 { /* NC */
1526 nvidia,pins = "clk3_req_pee1";
1527 nvidia,function = "rsvd2";
1528 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1529 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1530 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1531 };
1532 dap-mclk1-req-pee2 { /* NC */
1533 nvidia,pins = "dap_mclk1_req_pee2";
1534 nvidia,function = "rsvd4";
1535 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1536 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1537 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1538 };
1539 /*
1540 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
1541 * driver enabled aka not tristated and input driver
1542 * enabled as well as it features some magic properties
1543 * even though the external loopback is disabled and the
1544 * internal loopback used as per
1545 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1546 * bits being set to 0xfffd according to the TRM!
1547 */
1548 sdmmc3-clk-lb-out-pee4 { /* NC */
1549 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1550 nvidia,function = "sdmmc3";
1551 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1552 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1553 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1554 };
1555 };
1556 };
1557
1558 serial@70006040 {
1559 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1560 reset-names = "serial";
1561 /delete-property/ reg-shift;
1562 };
1563
1564 serial@70006200 {
1565 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1566 reset-names = "serial";
1567 /delete-property/ reg-shift;
1568 };
1569
1570 serial@70006300 {
1571 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1572 reset-names = "serial";
1573 /delete-property/ reg-shift;
1574 };
1575
1576 hdmi_ddc: i2c@7000c700 {
1577 clock-frequency = <10000>;
1578 };
1579
1580 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1581 i2c@7000d000 {
1582 status = "okay";
1583 clock-frequency = <400000>;
1584
1585 /* SGTL5000 audio codec */
1586 sgtl5000: codec@a {
1587 compatible = "fsl,sgtl5000";
1588 reg = <0x0a>;
1589 #sound-dai-cells = <0>;
1590 VDDA-supply = <®_module_3v3_audio>;
1591 VDDD-supply = <®_1v8_vddio>;
1592 VDDIO-supply = <®_1v8_vddio>;
1593 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1594 };
1595
1596 pmic: pmic@40 {
1597 compatible = "ams,as3722";
1598 reg = <0x40>;
1599 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1600 ams,system-power-controller;
1601 #interrupt-cells = <2>;
1602 interrupt-controller;
1603 gpio-controller;
1604 #gpio-cells = <2>;
1605 pinctrl-names = "default";
1606 pinctrl-0 = <&as3722_default>;
1607
1608 as3722_default: pinmux {
1609 gpio0-1-3-4-5-6 {
1610 pins = "gpio0", "gpio1", "gpio3",
1611 "gpio4", "gpio5", "gpio6";
1612 bias-high-impedance;
1613 };
1614
1615 gpio2-7 {
1616 pins = "gpio2", /* PWR_EN_+V3.3 */
1617 "gpio7"; /* +V1.6_LPO */
1618 function = "gpio";
1619 bias-pull-up;
1620 };
1621 };
1622
1623 regulators {
1624 vsup-sd2-supply = <®_module_3v3>;
1625 vsup-sd3-supply = <®_module_3v3>;
1626 vsup-sd4-supply = <®_module_3v3>;
1627 vsup-sd5-supply = <®_module_3v3>;
1628 vin-ldo0-supply = <®_1v35_vddio_ddr>;
1629 vin-ldo1-6-supply = <®_module_3v3>;
1630 vin-ldo2-5-7-supply = <®_1v8_vddio>;
1631 vin-ldo3-4-supply = <®_module_3v3>;
1632 vin-ldo9-10-supply = <®_module_3v3>;
1633 vin-ldo11-supply = <®_module_3v3>;
1634
1635 reg_vdd_cpu: sd0 {
1636 regulator-name = "+VDD_CPU_AP";
1637 regulator-min-microvolt = <700000>;
1638 regulator-max-microvolt = <1400000>;
1639 regulator-min-microamp = <3500000>;
1640 regulator-max-microamp = <3500000>;
1641 regulator-always-on;
1642 regulator-boot-on;
1643 ams,ext-control = <2>;
1644 };
1645
1646 sd1 {
1647 regulator-name = "+VDD_CORE";
1648 regulator-min-microvolt = <700000>;
1649 regulator-max-microvolt = <1350000>;
1650 regulator-min-microamp = <2500000>;
1651 regulator-max-microamp = <4000000>;
1652 regulator-always-on;
1653 regulator-boot-on;
1654 ams,ext-control = <1>;
1655 };
1656
1657 reg_1v35_vddio_ddr: sd2 {
1658 regulator-name =
1659 "+V1.35_VDDIO_DDR(sd2)";
1660 regulator-min-microvolt = <1350000>;
1661 regulator-max-microvolt = <1350000>;
1662 regulator-always-on;
1663 regulator-boot-on;
1664 };
1665
1666 sd3 {
1667 regulator-name =
1668 "+V1.35_VDDIO_DDR(sd3)";
1669 regulator-min-microvolt = <1350000>;
1670 regulator-max-microvolt = <1350000>;
1671 regulator-always-on;
1672 regulator-boot-on;
1673 };
1674
1675 reg_1v05_vdd: sd4 {
1676 regulator-name = "+V1.05";
1677 regulator-min-microvolt = <1050000>;
1678 regulator-max-microvolt = <1050000>;
1679 };
1680
1681 reg_1v8_vddio: sd5 {
1682 regulator-name = "+V1.8";
1683 regulator-min-microvolt = <1800000>;
1684 regulator-max-microvolt = <1800000>;
1685 regulator-boot-on;
1686 regulator-always-on;
1687 };
1688
1689 reg_vdd_gpu: sd6 {
1690 regulator-name = "+VDD_GPU_AP";
1691 regulator-min-microvolt = <650000>;
1692 regulator-max-microvolt = <1200000>;
1693 regulator-min-microamp = <3500000>;
1694 regulator-max-microamp = <3500000>;
1695 regulator-boot-on;
1696 regulator-always-on;
1697 };
1698
1699 reg_1v05_avdd: ldo0 {
1700 regulator-name = "+V1.05_AVDD";
1701 regulator-min-microvolt = <1050000>;
1702 regulator-max-microvolt = <1050000>;
1703 regulator-boot-on;
1704 regulator-always-on;
1705 ams,ext-control = <1>;
1706 };
1707
1708 vddio_sdmmc1: ldo1 {
1709 regulator-name = "VDDIO_SDMMC1";
1710 regulator-min-microvolt = <1800000>;
1711 regulator-max-microvolt = <3300000>;
1712 };
1713
1714 ldo2 {
1715 regulator-name = "+V1.2";
1716 regulator-min-microvolt = <1200000>;
1717 regulator-max-microvolt = <1200000>;
1718 regulator-boot-on;
1719 regulator-always-on;
1720 };
1721
1722 ldo3 {
1723 regulator-name = "+V1.05_RTC";
1724 regulator-min-microvolt = <1000000>;
1725 regulator-max-microvolt = <1000000>;
1726 regulator-boot-on;
1727 regulator-always-on;
1728 ams,enable-tracking;
1729 };
1730
1731 /* 1.8V for LVDS, 3.3V for eDP */
1732 ldo4 {
1733 regulator-name = "AVDD_LVDS0_PLL";
1734 regulator-min-microvolt = <1800000>;
1735 regulator-max-microvolt = <1800000>;
1736 };
1737
1738 /* LDO5 not used */
1739
1740 vddio_sdmmc3: ldo6 {
1741 regulator-name = "VDDIO_SDMMC3";
1742 regulator-min-microvolt = <1800000>;
1743 regulator-max-microvolt = <3300000>;
1744 };
1745
1746 /* LDO7 not used */
1747
1748 ldo9 {
1749 regulator-name = "+V3.3_ETH(ldo9)";
1750 regulator-min-microvolt = <3300000>;
1751 regulator-max-microvolt = <3300000>;
1752 regulator-always-on;
1753 };
1754
1755 ldo10 {
1756 regulator-name = "+V3.3_ETH(ldo10)";
1757 regulator-min-microvolt = <3300000>;
1758 regulator-max-microvolt = <3300000>;
1759 regulator-always-on;
1760 };
1761
1762 ldo11 {
1763 regulator-name = "+V1.8_VPP_FUSE";
1764 regulator-min-microvolt = <1800000>;
1765 regulator-max-microvolt = <1800000>;
1766 };
1767 };
1768 };
1769
1770 /*
1771 * TMP451 temperature sensor
1772 * Note: THERM_N directly connected to AS3722 PMIC THERM
1773 */
1774 temp-sensor@4c {
1775 compatible = "ti,tmp451";
1776 reg = <0x4c>;
1777 interrupt-parent = <&gpio>;
1778 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>;
1779 #thermal-sensor-cells = <1>;
1780 vcc-supply = <®_module_3v3>;
1781 };
1782 };
1783
1784 /* SPI2: MCU SPI */
1785 spi@7000d600 {
1786 status = "okay";
1787 spi-max-frequency = <25000000>;
1788 };
1789
1790 pmc@7000e400 {
1791 nvidia,invert-interrupt;
1792 nvidia,suspend-mode = <1>;
1793 nvidia,cpu-pwr-good-time = <500>;
1794 nvidia,cpu-pwr-off-time = <300>;
1795 nvidia,core-pwr-good-time = <641 3845>;
1796 nvidia,core-pwr-off-time = <61036>;
1797 nvidia,core-power-req-active-high;
1798 nvidia,sys-clock-req-active-high;
1799
1800 /* Set power_off bit in ResetControl register of AS3722 PMIC */
1801 i2c-thermtrip {
1802 nvidia,i2c-controller-id = <4>;
1803 nvidia,bus-addr = <0x40>;
1804 nvidia,reg-addr = <0x36>;
1805 nvidia,reg-data = <0x2>;
1806 };
1807 };
1808
1809 sata@70020000 {
1810 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1811 phy-names = "sata-0";
1812 avdd-supply = <®_1v05_vdd>;
1813 hvdd-supply = <®_module_3v3>;
1814 vddio-supply = <®_1v05_vdd>;
1815 };
1816
1817 usb@70090000 {
1818 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1819 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1820 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
1821 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1822 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1823 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1824 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1825
1826 avddio-pex-supply = <®_1v05_vdd>;
1827 avdd-pll-erefe-supply = <®_1v05_avdd>;
1828 avdd-pll-utmip-supply = <®_1v8_vddio>;
1829 avdd-usb-ss-pll-supply = <®_1v05_vdd>;
1830 avdd-usb-supply = <®_module_3v3>;
1831 dvddio-pex-supply = <®_1v05_vdd>;
1832 hvdd-usb-ss-pll-e-supply = <®_module_3v3>;
1833 hvdd-usb-ss-supply = <®_module_3v3>;
1834 };
1835
1836 padctl@7009f000 {
1837 avdd-pll-utmip-supply = <®_1v8_vddio>;
1838 avdd-pll-erefe-supply = <®_1v05_avdd>;
1839 avdd-pex-pll-supply = <®_1v05_vdd>;
1840 hvdd-pex-pll-e-supply = <®_module_3v3>;
1841
1842 pads {
1843 usb2 {
1844 status = "okay";
1845
1846 lanes {
1847 usb2-0 {
1848 status = "okay";
1849 nvidia,function = "xusb";
1850 };
1851
1852 usb2-1 {
1853 status = "okay";
1854 nvidia,function = "xusb";
1855 };
1856
1857 usb2-2 {
1858 status = "okay";
1859 nvidia,function = "xusb";
1860 };
1861 };
1862 };
1863
1864 pcie {
1865 status = "okay";
1866
1867 lanes {
1868 pcie-0 {
1869 status = "okay";
1870 nvidia,function = "usb3-ss";
1871 };
1872
1873 pcie-1 {
1874 status = "okay";
1875 nvidia,function = "usb3-ss";
1876 };
1877
1878 pcie-2 {
1879 status = "okay";
1880 nvidia,function = "pcie";
1881 };
1882
1883 pcie-3 {
1884 status = "okay";
1885 nvidia,function = "pcie";
1886 };
1887
1888 pcie-4 {
1889 status = "okay";
1890 nvidia,function = "pcie";
1891 };
1892 };
1893 };
1894
1895 sata {
1896 status = "okay";
1897
1898 lanes {
1899 sata-0 {
1900 status = "okay";
1901 nvidia,function = "sata";
1902 };
1903 };
1904 };
1905 };
1906
1907 ports {
1908 /* USBO1 */
1909 usb2-0 {
1910 status = "okay";
1911 mode = "otg";
1912 usb-role-switch;
1913 vbus-supply = <®_usbo1_vbus>;
1914 };
1915
1916 /* USBH2 */
1917 usb2-1 {
1918 status = "okay";
1919 mode = "host";
1920 vbus-supply = <®_usbh_vbus>;
1921 };
1922
1923 /* USBH4 */
1924 usb2-2 {
1925 status = "okay";
1926 mode = "host";
1927 vbus-supply = <®_usbh_vbus>;
1928 };
1929
1930 usb3-0 {
1931 status = "okay";
1932 nvidia,usb2-companion = <2>;
1933 vbus-supply = <®_usbh_vbus>;
1934 };
1935
1936 usb3-1 {
1937 status = "okay";
1938 nvidia,usb2-companion = <0>;
1939 vbus-supply = <®_usbo1_vbus>;
1940 };
1941 };
1942 };
1943
1944 /* eMMC */
1945 mmc@700b0600 {
1946 status = "okay";
1947 bus-width = <8>;
1948 non-removable;
1949 vmmc-supply = <®_module_3v3>; /* VCC */
1950 vqmmc-supply = <®_1v8_vddio>; /* VCCQ */
1951 mmc-ddr-1_8v;
1952 };
1953
1954 /* CPU DFLL clock */
1955 clock@70110000 {
1956 status = "okay";
1957 nvidia,i2c-fs-rate = <400000>;
1958 vdd-cpu-supply = <®_vdd_cpu>;
1959 };
1960
1961 ahub@70300000 {
1962 i2s@70301200 {
1963 status = "okay";
1964 };
1965 };
1966
1967 cpus {
1968 cpu@0 {
1969 vdd-cpu-supply = <®_vdd_cpu>;
1970 };
1971 };
1972
1973 clk32k_in: osc3 {
1974 compatible = "fixed-clock";
1975 #clock-cells = <0>;
1976 clock-frequency = <32768>;
1977 };
1978
1979 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
1980 compatible = "regulator-fixed";
1981 regulator-name = "+V1.05_AVDD_HDMI_PLL";
1982 regulator-min-microvolt = <1050000>;
1983 regulator-max-microvolt = <1050000>;
1984 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1985 vin-supply = <®_1v05_vdd>;
1986 };
1987
1988 reg_3v3_mxm: regulator-3v3-mxm {
1989 compatible = "regulator-fixed";
1990 regulator-name = "+V3.3_MXM";
1991 regulator-min-microvolt = <3300000>;
1992 regulator-max-microvolt = <3300000>;
1993 regulator-always-on;
1994 regulator-boot-on;
1995 };
1996
1997 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1998 compatible = "regulator-fixed";
1999 regulator-name = "+V3.3_AVDD_HDMI";
2000 regulator-min-microvolt = <3300000>;
2001 regulator-max-microvolt = <3300000>;
2002 vin-supply = <®_1v05_vdd>;
2003 };
2004
2005 reg_module_3v3: regulator-module-3v3 {
2006 compatible = "regulator-fixed";
2007 regulator-name = "+V3.3";
2008 regulator-min-microvolt = <3300000>;
2009 regulator-max-microvolt = <3300000>;
2010 regulator-always-on;
2011 regulator-boot-on;
2012 /* PWR_EN_+V3.3 */
2013 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
2014 enable-active-high;
2015 vin-supply = <®_3v3_mxm>;
2016 };
2017
2018 reg_module_3v3_audio: regulator-module-3v3-audio {
2019 compatible = "regulator-fixed";
2020 regulator-name = "+V3.3_AUDIO_AVDD_S";
2021 regulator-min-microvolt = <3300000>;
2022 regulator-max-microvolt = <3300000>;
2023 regulator-always-on;
2024 };
2025
2026 sound {
2027 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
2028 "nvidia,tegra-audio-sgtl5000";
2029 nvidia,model = "Toradex Apalis TK1";
2030 nvidia,audio-routing =
2031 "Headphone Jack", "HP_OUT",
2032 "LINE_IN", "Line In Jack",
2033 "MIC_IN", "Mic Jack";
2034 nvidia,i2s-controller = <&tegra_i2s2>;
2035 nvidia,audio-codec = <&sgtl5000>;
2036 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2037 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2038 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
2039 clock-names = "pll_a", "pll_a_out0", "mclk";
2040
2041 assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
2042 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
2043
2044 assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2045 <&tegra_car TEGRA124_CLK_EXTERN1>;
2046 };
2047
2048 thermal-zones {
2049 cpu-thermal {
2050 trips {
2051 cpu-shutdown-trip {
2052 temperature = <101000>;
2053 hysteresis = <0>;
2054 type = "critical";
2055 };
2056 };
2057 };
2058
2059 mem-thermal {
2060 trips {
2061 mem-shutdown-trip {
2062 temperature = <101000>;
2063 hysteresis = <0>;
2064 type = "critical";
2065 };
2066 };
2067 };
2068
2069 gpu-thermal {
2070 trips {
2071 gpu-shutdown-trip {
2072 temperature = <101000>;
2073 hysteresis = <0>;
2074 type = "critical";
2075 };
2076 };
2077 };
2078 };
2079 };
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