1 // SPDX-License-Identifier: GPL-2.0
2
3 #include "tegra30-asus-nexus7-grouper-common.dtsi"
4 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
5
6 / {
7 compatible = "asus,grouper", "nvidia,tegra30";
8
9 pinmux@70000868 {
10 state_default: pinmux {
11 lcd_dc1_pd2 {
12 nvidia,pins = "lcd_dc1_pd2";
13 nvidia,function = "displaya";
14 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
15 nvidia,tristate = <TEGRA_PIN_DISABLE>;
16 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
17 };
18 lcd_pwr2_pc6 {
19 nvidia,pins = "lcd_pwr2_pc6";
20 nvidia,function = "displaya";
21 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
22 nvidia,tristate = <TEGRA_PIN_DISABLE>;
23 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
24 };
25 spi2_cs2_n_pw3 {
26 nvidia,pins = "spi2_cs2_n_pw3";
27 nvidia,function = "spi2";
28 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
29 nvidia,tristate = <TEGRA_PIN_DISABLE>;
30 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
31 };
32 spi1_sck_px5 {
33 nvidia,pins = "spi1_sck_px5";
34 nvidia,function = "spi1";
35 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
36 nvidia,tristate = <TEGRA_PIN_DISABLE>;
37 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
38 };
39 pu5 {
40 nvidia,pins = "pu5";
41 nvidia,function = "pwm2";
42 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
43 nvidia,tristate = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
45 };
46 spi1_miso_px7 {
47 nvidia,pins = "spi1_miso_px7";
48 nvidia,function = "spi1";
49 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
50 nvidia,tristate = <TEGRA_PIN_DISABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
52 };
53 spi2_mosi_px0 {
54 nvidia,pins = "spi2_mosi_px0";
55 nvidia,function = "spi2";
56 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
57 nvidia,tristate = <TEGRA_PIN_DISABLE>;
58 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
59 };
60 kb_row7_pr7 {
61 nvidia,pins = "kb_row7_pr7";
62 nvidia,function = "kbc";
63 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
64 nvidia,tristate = <TEGRA_PIN_DISABLE>;
65 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
66 };
67 pu3 {
68 nvidia,pins = "pu3";
69 nvidia,function = "rsvd4";
70 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
71 nvidia,tristate = <TEGRA_PIN_DISABLE>;
72 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
73 };
74 pu4 {
75 nvidia,pins = "pu4";
76 nvidia,function = "pwm1";
77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_ENABLE>;
79 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
80 };
81 kb_row15_ps7 {
82 nvidia,pins = "kb_row15_ps7";
83 nvidia,function = "kbc";
84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
86 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
87 };
88 kb_row3_pr3 {
89 nvidia,pins = "kb_row3_pr3";
90 nvidia,function = "kbc";
91 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
92 nvidia,tristate = <TEGRA_PIN_DISABLE>;
93 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
94 };
95 kb_row13_ps5 {
96 nvidia,pins = "kb_row13_ps5";
97 nvidia,function = "kbc";
98 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
99 nvidia,tristate = <TEGRA_PIN_ENABLE>;
100 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
101 };
102 gmi_wp_n_pc7 {
103 nvidia,pins = "gmi_wp_n_pc7",
104 "gmi_wait_pi7",
105 "gmi_cs4_n_pk2",
106 "gmi_cs3_n_pk4";
107 nvidia,function = "rsvd1";
108 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
109 nvidia,tristate = <TEGRA_PIN_ENABLE>;
110 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
111 };
112 gmi_cs6_n_pi3 {
113 nvidia,pins = "gmi_cs6_n_pi3";
114 nvidia,function = "gmi";
115 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
116 nvidia,tristate = <TEGRA_PIN_ENABLE>;
117 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
118 };
119 };
120 };
121
122 i2c@7000c500 {
123 nfc@28 {
124 compatible = "nxp,pn544-i2c";
125 reg = <0x28>;
126
127 interrupt-parent = <&gpio>;
128 interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_EDGE_RISING>;
129
130 enable-gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
131 firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
132 };
133 };
134
135 display-panel {
136 panel-timing {
137 clock-frequency = <68000000>;
138 hactive = <800>;
139 vactive = <1280>;
140 hfront-porch = <24>;
141 hback-porch = <32>;
142 hsync-len = <24>;
143 vsync-len = <1>;
144 vfront-porch = <5>;
145 vback-porch = <32>;
146 };
147 };
148 };
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